A Dual-Edge-Triggered (DET) flip-flop (FF) that can reliably operate at low voltage is
proposed in this paper. Unlike the conventional Single-Edge-Triggered (SET) flip-flops, DET …

This paper presents novel designs of static dual-edge-triggered (DET) flip-flops that exhibit
unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are …

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has
become one of the most power-hungry blocks in processors. To address this issue, a novel …

Power utilization assumes a massive part in any of the integrated circuits, and it's rundown
as a standout amongst essential difficulties in the universal innovation guide into …

In order to meet the growing demand for energy-efficient devices, particularly in portable and
battery-powered applications, low-power flip-flop designs are crucial in modern electronics …

F1ip-flops/pulsed latches are one of the main contributors of power consumption in modern
processors including GPU/AI processors. In this paper, a novel Low-Power Explicit-Pulsed …

For low-power, high-performance circuits, dual edge triggered (DET) synchronized
operation is highly attractive. When paired with half the clock frequency, DET operation can …

Dual Edge Triggered Flip Flop (DET FF) is a sequential circuit element that record data at
both the positive and negative edges of the clock signal which results in faster throughput in …

Dual edge triggered (DET) techniques are most liked choice for the researchers in the field
of digital VLSI design because of its high‐performance and low‐power consumption …

A shallow-depth differential source coupled logic is proposed in this paper, targeting low-
voltage high-speed applications. In this logic, the number of transistor stages decreases …