Review of neural network model acceleration techniques based on FPGA platforms
F Liu, H Li, W Hu, Y He - Neurocomputing, 2024 - Elsevier
Neural network models, celebrated for their outstanding scalability and computational
capabilities, have demonstrated remarkable performance across various fields such as …
capabilities, have demonstrated remarkable performance across various fields such as …
Large circuit models: opportunities and challenges
Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven
solutions have emerged as formidable tools, yet they typically augment rather than redefine …
solutions have emerged as formidable tools, yet they typically augment rather than redefine …
High-level synthesis hardware design for fpga-based accelerators: Models, methodologies, and frameworks
Hardware accelerators based on field programmable gate array (FPGA) and system on chip
(SoC) devices have gained attention in recent years. One of the main reasons is that these …
(SoC) devices have gained attention in recent years. One of the main reasons is that these …
The dawn of ai-native eda: Promises and challenges of large circuit models
L Chen, Y Chen, Z Chu, W Fang, TY Ho… - ar** of multi-output functions leading to the reduction of dynamic power consumption in FPGAs
A Opara, M Kubica - International Journal of Applied …, 2023 - intapi.sciendo.com
This article presents a synthesis strategy aimed at minimizing the dynamic power
consumption of combinational circuits mapped in LUT blocks of FPGAs. The implemented …
consumption of combinational circuits mapped in LUT blocks of FPGAs. The implemented …
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for
quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the …
quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the …