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A technological and electrical study of self-aligned charge-trap split-gate memory devices
C Charpin-Nicolle, A De Luca, A Persico… - Microelectronic …, 2014 - Elsevier
In this work, self-aligned charge trap split-gate devices with memory gate lengths down to 16
nm and select gate lengths down to 30 nm are fabricated and studied. Main technological …
nm and select gate lengths down to 30 nm are fabricated and studied. Main technological …
Optimization of programming consumption of silicon nanocrystal memories for low power applications
V Della Marca, L Masoero, G Molas… - 2012 International …, 2012 - ieeexplore.ieee.org
In this paper we propose the optimization of the programming operation scheme of Silicon
nanocrystal (Si-nc) memories in order to reduce the energy consumption for low power …
nanocrystal (Si-nc) memories in order to reduce the energy consumption for low power …
Etude d'architectures et d'empilements innovants de mémoires Split-Gate (grille séparée) à couche de piégeage discret
L Masoero - 2012 - theses.hal.science
Du fait de l'augmentation de la demande de produits pour les applications grand public,
industrielles et automobiles, des mémoires embarquées fiables et à faible coût de …
industrielles et automobiles, des mémoires embarquées fiables et à faible coût de …
[TRÍCH DẪN][C] 一种改进的 SOI Flash 存储器
孙跃， 陈德媛， 何源君， 王媛媛， 章纲 - 微电子学, 2015
[TRÍCH DẪN][C] C. Charpin-Nicolle “, A. de Luca, A. Persico, G. Médico, C. Tallaron, F. Aussenac, R. Kies, G. Molas
L Masoero, O Cueto, B de Salvo - Microelectronic Engineering, 2014