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[کتاب][B] Handbook of signal processing systems
SS Bhattacharyya, EF Deprettere, R Leupers, J Takala - 2018 - books.google.com
In this new edition of the Handbook of Signal Processing Systems, many of the chapters
from the previous editions have been updated, and several new chapters have been added …
from the previous editions have been updated, and several new chapters have been added …
Coarse-grained reconfigurable array architectures
Abstract Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same
inner loops that benefit from the high instruction-level parallelism (ILP) support in very long …
inner loops that benefit from the high instruction-level parallelism (ILP) support in very long …
A RISC-V ISA extension for ultra-low power IoT wireless signal processing
HB Amor, C Bernier, Z Přikryl - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This article presents an instruction-set extension to the open-source RISC-V ISA (RV32IM)
dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom …
dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom …
A heterogeneous SDR MPSoC in 28 nm CMOS for low-latency wireless applications
Current and future applications impose high demands on software-defined radio (SDR)
platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous …
platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous …
Optimization of communication schemes for DMA-controlled accelerators
The hardware accelerator controlled by direct memory access (DMA) is greatly influenced by
the communication bandwidth from/to DRAM through on-chip buses. This paper proposes a …
the communication bandwidth from/to DRAM through on-chip buses. This paper proposes a …
A bimodal scheduler for coarse-grained reconfigurable arrays
Compilers for Course-Grained Reconfigurable Array (CGRA) architectures suffer from long
compilation times and code quality levels far below the theoretical upper bounds. This article …
compilation times and code quality levels far below the theoretical upper bounds. This article …
A 4 4 MIMO-OFDM Baseband Receiver With 160 MHz Bandwidth for Indoor Gigabit Wireless Communications
PY Tsai, PC Lo, FJ Shih, WJ Jau… - … on Circuits and …, 2015 - ieeexplore.ieee.org
This paper presents the design and implementation of a 4× 4 multiple-input multiple-output
orthogonal frequency division multiplexing (MIMO-OFDM) baseband receiver for indoor high …
orthogonal frequency division multiplexing (MIMO-OFDM) baseband receiver for indoor high …
Trends of communication processors
L Dake, C Zhaoyun, W Wei - China Communications, 2016 - ieeexplore.ieee.org
Processors have been playing important roles in both communication infrastructure systems
and terminals. In this paper, both application specific and general purpose processors for …
and terminals. In this paper, both application specific and general purpose processors for …
An implementation of multiple-standard video decoder on a mixed-grained reconfigurable computing platform
This paper presents the design of a multiple-standard 1080 high definition (HD) video
decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained …
decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained …
Early exploration for platform architecture instantiation with multi-mode application partitioning
We present a systematic methodology for exploring application partitioning and assignment
together with platform architecture instantiation. Streaming applications with multiple runtime …
together with platform architecture instantiation. Streaming applications with multiple runtime …