Pads and pin-outs in three dimensional integrated circuits
RU Madurawe - US Patent 9,070,668, 2015 - Google Patents
US9070668B2 - Pads and pin-outs in three dimensional integrated circuits - Google Patents
US9070668B2 - Pads and pin-outs in three dimensional integrated circuits - Google Patents …
US9070668B2 - Pads and pin-outs in three dimensional integrated circuits - Google Patents …
Three dimensional integrated circuits
RU Madurawe - US Patent 8,829,664, 2014 - Google Patents
A three-dimensional semiconductor device, comprising: a first module layer having a
plurality of circuit blocks; and a second module layer positioned substantially above the first …
plurality of circuit blocks; and a second module layer positioned substantially above the first …
Cell circuit and layout with linear finfet structures
ST Becker - US Patent 9,563,733, 2017 - Google Patents
(57) ABSTRACT A cell circuit and corresponding layout is disclosed to include linear-
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
shaped diffusion fins defined to extend over a Substrate in a first direction so as to extend …
High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline
JZ Peng - US Patent 6,992,925, 2006 - Google Patents
A programmable memory cell comprised of a transistor located at the crosspoint of a column
bitline and a row wordline is disclosed. The transistor has its gate formed from the column …
bitline and a row wordline is disclosed. The transistor has its gate formed from the column …
Finfet transistor circuit
ST Becker, MC Smayling, D Gandhi, J Mali… - US Patent …, 2014 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate …
ST Becker, MC Smayling - US Patent 7,923,757, 2011 - Google Patents
(57) ABSTRACT A restricted layout region includes a diffusion level layout including p-type
and n-type diffusion region layout shapes separated by a central inactive region. The …
and n-type diffusion region layout shapes separated by a central inactive region. The …
Dynamic array architecture
ST Becker, MC Smayling - US Patent 7,446,352, 2008 - Google Patents
5,923,059 A 7/1999 Gheewala................... 257/204 of the substrate. The semiconductor
device includes a number of linear gate electrode tracks de? ned to extend over the …
device includes a number of linear gate electrode tracks de? ned to extend over the …
Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions
ST Becker, MC Smayling - US Patent 7,906,801, 2011 - Google Patents
(57) ABSTRACT A restricted layout region is defined to include a diffusion level layout that
includes a plurality of diffusion region layout shapes to be formed within a portion of a …
includes a plurality of diffusion region layout shapes to be formed within a portion of a …
Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions
ST Becker, MC Smayling - US Patent 7,932,544, 2011 - Google Patents
(57) ABSTRACT A restricted layout region in a layout of a semiconductor device is disclosed
to include a diffusion level layout includ ing a plurality of diffusion region layout shapes. The …
to include a diffusion level layout includ ing a plurality of diffusion region layout shapes. The …
Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment
ST Becker, MC Smayling - US Patent 7,910,958, 2011 - Google Patents
(57) ABSTRACT A semiconductor device is disclosed as having a substrate portion that
includes a plurality of diffusion regions that include at least one p-type diffusion region and …
includes a plurality of diffusion regions that include at least one p-type diffusion region and …