Effect of band-to-band tunneling on junctionless transistors
We evaluate the impact of band-to-band tunneling (BTBT) on the characteristics of n-
channel junctionless transistors (JLTs). A JLT that has a heavily doped channel, which is …
channel junctionless transistors (JLTs). A JLT that has a heavily doped channel, which is …
Effect of gate engineering in double-gate MOSFETs for analog/RF applications
This work uncovers the potential benefit of fully-depleted short-channel triple-material
double-gate (TM-DG) SOI MOSFET in the context of RF and analog performance …
double-gate (TM-DG) SOI MOSFET in the context of RF and analog performance …
A junctionless nanowire transistor with a dual-material gate
A dual-material-gate junctionless nanowire transistor (DMG-JNT) is proposed in this paper.
Its characteristic is demonstrated and compared with a generic single-material-gate JNT …
Its characteristic is demonstrated and compared with a generic single-material-gate JNT …
A Dual-Material Gate Junctionless Transistor With High- Spacer for Enhanced Analog Performance
RK Baruah, RP Paily - IEEE Transactions on electron devices, 2013 - ieeexplore.ieee.org
In this paper, we present a simulation study of analog circuit performance parameters for a
symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with …
symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with …
Semianalytical model of the subthreshold current in short-channel junctionless symmetric double-gate field-effect transistors
A Gnudi, S Reggiani, E Gnani… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric
double-gate field-effect transistors in subthreshold regime is proposed, which is based on …
double-gate field-effect transistors in subthreshold regime is proposed, which is based on …
High-performance junctionless MOSFETs for ultralow-power analog/RF applications
In this letter, we demonstrate the usefulness of ultralow-power (ULP) junctionless (JL)
MOSFETs in achieving improved analog/RF metrics as compared to nonunderlap and …
MOSFETs in achieving improved analog/RF metrics as compared to nonunderlap and …
Impact of gate material engineering (GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless …
Abstract In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire
Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack …
Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack …
Performance evaluation and reliability issues of junctionless CSG MOSFET for RFIC design
This paper investigates the reliability issues of junctionless cylindrical surrounding-gate (JL
CSG) MOSFET by employing temperature variations, ranging from 200 K to 500 K, along …
CSG) MOSFET by employing temperature variations, ranging from 200 K to 500 K, along …
[BOOK][B] Modeling nanowire and double-gate junctionless field-effect transistors
F Jazaeri, JM Sallese - 2018 - books.google.com
The first book on the topic, this is a comprehensive introduction to the modeling and design
of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages …
of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages …
A vertically integrated junctionless nanowire transistor
A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of
vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure …
vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure …