Dcryp-unit: Crypto hardware accelerator unit design for elliptic curve point multiplication

AR Alharbi, MM Hazzazi, SS Jamal, A Aljaedi… - IEEE …, 2024 - ieeexplore.ieee.org
We propose a hardware-optimized design that implements a Montgomery Elliptic-curve
point multiplication Algorithm over using Lopez-Dahab projective coordinates. Moreover, we …

Unif-NTT: A unified hardware design of forward and inverse NTT for PQC algorithms

AY Hummdi, A Aljaedi, Z Bassfar, SS Jamal… - IEEE …, 2024 - ieeexplore.ieee.org
Polynomial multiplications based on the number theoretic transform (NTT) are critical in
lattice-based post-quantum cryptography algorithms. Therefore, this paper presents a …

High-speed design of post quantum cryptography with optimized hashing and multiplication

M Imran, A Aikata, SS Roy… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
In this brief, we realize different architectural techniques for improving the performance of
post-quantum cryptography (PQC) algorithms when implemented as hardware accelerators …

A 334 μW 0.158 mm2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding Toom–Cook Multiplication

A Ghosh, JMB Mera, A Karmakar, D Das… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
Lattice-based cryptography is a novel approach to public key cryptography (PKC), of which
the mathematical investigation (so far) resists attacks from quantum computers. By choosing …

REPQC: Reverse Engineering and Backdooring Hardware Accelerators for Post-quantum Cryptography

S Pagliarini, A Aikata, M Imran… - Proceedings of the 19th …, 2024 - dl.acm.org
Significant research efforts have been dedicated to designing cryptographic algorithms that
are quantum-resistant. The motivation is clear: robust quantum computers, once available …

Area-Efficient Realization of Binary Elliptic Curve Point Multiplication Processor for Cryptographic Applications

A Aljaedi, SS Jamal, M Rashid, AR Alharbi, M Alotaibi… - Applied Sciences, 2023 - mdpi.com
This paper proposes a novel hardware design for a compact crypto processor devoted to
elliptic-curve point multiplication over GF (2 233). We focus on minimizing hardware usage …

A Flexible and Parallel Hardware Accelerator for Forward and Inverse Number Theoretic Transform

M Rashid, S Khan, OS Sonbul, SO Hwang - IEEE Access, 2024 - ieeexplore.ieee.org
This paper demonstrates an efficient and flexible hardware accelerator for polynomial
multiplication using number theoretic transform (NTT). The proposed architecture considers …

A Pipelined Hardware Design of FNTT and INTT of CRYSTALS-Kyber PQC Algorithm.

M Rashid, OS Sonbul, SS Jamal… - Information (2078 …, 2025 - search.ebscohost.com
Lattice-based post-quantum cryptography (PQC) algorithms demand number theoretic
transform (NTT)-based polynomial multiplications. NTT-based polynomials' multiplication …

Saber with Hybrid Striding Toom Cook-based Multiplier: Implementation Using Open-Source Tool Flow and Industry Standard Chip Design Tools

MN Abbasi, AR Aslam, MAB Altaf, W Saadeh - IEEE Access, 2024 - ieeexplore.ieee.org
Quantum computers are a significant threat to the existing cryptography algorithms. The
Saber is a lattice-based post-quantum cryptographic or quantum-safe algorithm designed as …

Towards high-speed asic implementations of post-quantum cryptography

M Imran, A Aikata, SS Roy - Cryptology ePrint Archive, 2023 - eprint.iacr.org
In this brief, we realize different architectural techniques towards improving the performance
of post-quantum cryptography (PQC) algorithms when implemented as hardware …