Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation
Two major trends in high-performance computing, namely, larger numbers of cores and the
growing size of on-chip cache memory, are creating significant challenges for evaluating the …
growing size of on-chip cache memory, are creating significant challenges for evaluating the …
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
GPU architectures are increasingly important in the multi-core era due to their high number
of parallel processors. Programming thousands of massively parallel threads is a big …
of parallel processors. Programming thousands of massively parallel threads is a big …
A first-order superscalar processor model
TS Karkhanis, JE Smith - ACM SIGARCH Computer Architecture News, 2004 - dl.acm.org
A proposed performance model for superscalar processorsconsists of 1) a component that
models the relationshipbetween instructions issued per cycle and the sizeof the instruction …
models the relationshipbetween instructions issued per cycle and the sizeof the instruction …
Microarchitecture optimizations for exploiting memory-level parallelism
Y Chou, B Fahs, S Abraham - ACM SIGARCH Computer Architecture …, 2004 - dl.acm.org
The performance of memory-bound commercial applicationssuch as databases is limited by
increasing memory latencies. Inthis paper, we show that exploiting memory-level parallelism …
increasing memory latencies. Inthis paper, we show that exploiting memory-level parallelism …
A mechanistic performance model for superscalar out-of-order processors
A mechanistic model for out-of-order superscalar processors is developed and then applied
to the study of microarchitecture resource scaling. The model divides execution time into …
to the study of microarchitecture resource scaling. The model divides execution time into …
Interval simulation: Raising the level of abstraction in architectural simulation
D Genbrugge, S Eyerman… - HPCA-16 2010 The …, 2010 - ieeexplore.ieee.org
Detailed architectural simulators suffer from a long development cycle and extremely long
evaluation times. This longstanding problem is further exacerbated in the multi-core …
evaluation times. This longstanding problem is further exacerbated in the multi-core …
[KNJIGA][B] Computer architecture performance evaluation methods
L Eeckhout - 2010 - books.google.com
Performance evaluation is at the foundation of computer architecture research and
development. Contemporary microprocessors are so complex that architects cannot design …
development. Contemporary microprocessors are so complex that architects cannot design …
Predicting performance impact of DVFS for realistic memory systems
Dynamic voltage and frequency scaling (DVFS) can make modern processors more power
and energy efficient if we can accurately predict the effect of frequency scaling on processor …
and energy efficient if we can accurately predict the effect of frequency scaling on processor …
[KNJIGA][B] Performance evaluation and benchmarking
LK John, L Eeckhout - 2018 - taylorfrancis.com
Computer and microprocessor architectures are advancing at an astounding pace.
However, increasing demands on performance coupled with a wide variety of specialized …
However, increasing demands on performance coupled with a wide variety of specialized …
Accurate phase-level cross-platform power and performance estimation
Fast and accurate performance and power prediction is a key challenge in co-development
of hardware and software. Traditional analytical or simulation-based approaches are often …
of hardware and software. Traditional analytical or simulation-based approaches are often …