System-level power optimization: techniques and tools

L Benini, G Micheli - ACM Transactions on Design Automation of …, 2000 - dl.acm.org
This tutorial surveys design methods for energy-efficient system-level design. We consider
electronic sytems consisting of a hardware platform and software layers. We consider the …

Memory bus encoding for low power: a tutorial

WC Cheng, M Pedram - Proceedings of the IEEE 2001. 2nd …, 2001 - ieeexplore.ieee.org
This paper contains a tutorial on bus-encoding techniques that target low power dissipation.
Three general classes of codes, ie, algebraic, permutation-based, and probability-based …

[LIBRO][B] On-chip communication architectures: system on chip interconnect

S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

A subexponential algorithm for the discrete logarithm problem with applications to cryptography

L Adleman - 20th Annual Symposium on Foundations of Computer …, 1979 - computer.org
In this paper we describe a new method for encoding data streams on system buses in order
to reduce bus line transition activity. Our focus is on data streams whose statistical …

[LIBRO][B] Multiprocessor systems-on-chips

A Jerraya, W Wolf - 2004 - books.google.com
Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …

[LIBRO][B] Computer architecture techniques for power-efficiency

S Kaxiras, M Martonosi - 2008 - books.google.com
In the last few years, power dissipation has become an important design constraint, on par
with performance, in the design of new computer systems. Whereas in the past, the primary …

[LIBRO][B] Dynamic power management: design techniques and CAD tools

L Benini, G DeMicheli - 2012 - books.google.com
Dynamic power management is a design methodology aiming at controlling performance
and power levels of digital circuits and systems, with the goal of extending the autonomous …

High-level power modeling, estimation, and optimization

E Macii, M Pedram, F Somenzi - Proceedings of the 34th annual Design …, 1997 - dl.acm.org
In the past, the major concern of the VLSI designers werearea, performance, cost, and
reliability. In recent years, however, this has changed and, increasingly, power is beinggiven …

A coding framework for low-power address and data busses

S Ramprasad, NR Shanbhag… - IEEE Transactions on Very …, 2002 - ieeexplore.ieee.org
This paper presents a source-coding framework for the design of coding schemes to reduce
transition activity. These schemes are suited for high-capacitance buses where the extra …

Coding for racetrack memories

YM Chee, HM Kiah, A Vardy… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Racetrack memory is a new technology, which utilizes magnetic domains along a
nanoscopic wire in order to obtain extremely high storage density. In racetrack memory …