The ever-increasing quest for data-level parallelism and variable precision in ubiquitous
multimedia and Deep Neural Network (DNN) applications has motivated the use of Single …

This paper presents an architecture and implementation details for MORA, a novel coarse
grained reconfigurable processor for accelerating media processing applications. The …

This paper presents an FPGA implementation of a low cost 8 bit reconfigurable processor
core for media processing applications. The core is optimized to provide all basic arithmetic …

This paper presents the design, the analysis and the complete characterization of a novel
split-path Data Driven Dynamic (sp-D3L) full adder cell in IBM's 65 nm CMOS process. The …

We present the architecture and programming model for MORA, a coarse-grained
reconfigurable processor aimed at multimedia applications. The MORA architecure is a …

The saturation of design complexity and clock frequencies for single-core processors has
resulted in the emergence of multicore architectures as an alternative design paradigm …

Reconfigurable computing for DSP remains an active area to explore as the need for
incorporation with more conventional DSP technologies turn out to be obvious …

In this paper, we present the design and implementation of a reconfigurable finite impulse
response (FIR) filter for adaptive systems with online fault detection mechanism. An area …

Reconfigurable computing for DSP remains an active area of research as the need for
integration with more traditional DSP technologies become apparent. Traditionally, most of …

Semiconductor technology improvements enable designers to integrate complex systems
composed of tens and even hundreds of modules (blocks or components) into a single chip …