Microprocessor aging analysis and reliability modeling due to back-end wearout mechanisms
Back-end wearout mechanisms are major reliability concerns for modern microprocessors.
In this paper, a framework that contains modules for back-end time-dependent dielectric …
In this paper, a framework that contains modules for back-end time-dependent dielectric …
System-level modeling of microprocessor reliability degradation due to bias temperature instability and hot carrier injection
Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and
hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this …
hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this …
Comprehensive reliability and aging analysis on SRAMs within microprocessor systems
A framework is proposed to analyze the impact of both Front End of the Line (FEOL) and
Back End of the Line (BEOL) wearout mechanisms on memories embedded within state-of …
Back End of the Line (BEOL) wearout mechanisms on memories embedded within state-of …
Memory and logic lifetime simulation systems and methods
Aspects of the disclosed technology include a method including extracting, by a processor, a
plurality of features from one from among a layout of a circuit, a netlist of the circuit, and the …
plurality of features from one from among a layout of a circuit, a netlist of the circuit, and the …
Processor-level reliability simulator for time-dependent gate dielectric breakdown
Time-dependent gate dielectric breakdown (TDDB) is a leading reliability concern for
modern microprocessors. In this paper, a framework is proposed to analyze the impact of …
modern microprocessors. In this paper, a framework is proposed to analyze the impact of …
Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations
Time dependent dielectric breakdown degrades the reliability of SRAM cache. A novel
methodology to estimate SRAM cache reliability and performance is presented. The …
methodology to estimate SRAM cache reliability and performance is presented. The …
Estimation of the optimal accelerated test region for FinFET SRAMs degraded by front-end and back-end wearout mechanisms
Advanced FinFET SRAMs undergo reliability degradation due to various front-end and back-
end wearout mechanisms. The design of reliable SRAMs benefits from accurate wearout …
end wearout mechanisms. The design of reliable SRAMs benefits from accurate wearout …
System-level modeling of microprocessor reliability degradation due to TDDB
Time-dependent dielectric breakdown (TDDB) is leading reliability concerns for modern
microprocessors. In this paper, a framework is proposed to analyze the impact of TDDB on …
microprocessors. In this paper, a framework is proposed to analyze the impact of TDDB on …