An efficient application map** approach for the co-optimization of reliability, energy, and performance in reconfigurable NoC architectures
In this paper, an efficient application map** approach is proposed for the co-optimization
of reliability, communication energy, and performance (CoREP) in network-on-chip (NoC) …
of reliability, communication energy, and performance (CoREP) in network-on-chip (NoC) …
KL_GA: an application map** algorithm for mesh-of-tree (MoT) architecture in network-on-chip design
J Fang, L Yu, S Liu, J Lu, T Chen - The Journal of Supercomputing, 2015 - Springer
As the very large-scale integrated circuit designs enter the deep sub-micron era, many-core
processors are regarded as promising architectures to keep up with the Moore's law. To …
processors are regarded as promising architectures to keep up with the Moore's law. To …
Optimized map** spiking neural networks onto network-on-chip
Map** spiking neural networks (SNNs) onto network-on-chips (NoCs) is pivotal to fully
utilize the hardware resources of dedicated multi-core processors (CMPs) for SNNs' …
utilize the hardware resources of dedicated multi-core processors (CMPs) for SNNs' …
KGT: An Application Map** Algorithm Based on Kernighan–Lin Partition and Genetic Algorithm for WK-Recursive NoC Architecture
H Zhang, X Wang - Intelligent Computing Theories and Application: 17th …, 2021 - Springer
Some previous researches have explored the application map**s for network-on-chip to
reduce the power consumption and the network latency. However, some of these previous …
reduce the power consumption and the network latency. However, some of these previous …
Map** of embedded applications on hybrid networks-on-chip with multiple switching mechanisms
G Jiang, Z Li, F Wang, S Wei - IEEE Embedded Systems Letters, 2015 - ieeexplore.ieee.org
This letter aims at optimizing the map** of embedded applications on the hybrid network-
on-chip (NoC) that intermingles multiple switching mechanisms. Specifically, we identify the …
on-chip (NoC) that intermingles multiple switching mechanisms. Specifically, we identify the …
Traffic-aware application map** for network-on-chip based multiprocessor system-on-chip
Network on Chip (NoC) has become a promising solution for the communication paradigm
of the next-generation multiprocessor system-on-chip (MPSoC). As communication has …
of the next-generation multiprocessor system-on-chip (MPSoC). As communication has …
Maximizing the performance of NoC-based MPSoCs under total power and power density constraints
This paper presents an application map** problem, which aims to maximize the
performance of NoC-based multi-processor system-on-chip (MPSoC) designs without …
performance of NoC-based multi-processor system-on-chip (MPSoC) designs without …
KLSAT: An application map** algorithm based on Kernighan–Lin partition and simulated annealing for a specific WK-recursive NoC architecture
X Wang, F Shi, H Zhang - IFIP International Conference on Network and …, 2019 - Springer
Application map** is a critical phase in NoC design because of the running time, the
network latency and the power consumption. In order to reduce these problems of …
network latency and the power consumption. In order to reduce these problems of …
Mitigating transceiver and token controller permanent faults in wireless network-on-chip
Conventional wired Network-on-Chip (NoC) designs suffer from performance degradation
due to multi-hop long-distance communication. To address such a problem, in the past …
due to multi-hop long-distance communication. To address such a problem, in the past …
Providing balanced map** for multiple applications in many-core chip multiprocessors
This paper addresses the problem of balancing the on-chip packet latencies in a chip multi-
processor (CMP), which is simultaneously executing multiple applications. Specifically, this …
processor (CMP), which is simultaneously executing multiple applications. Specifically, this …