(57) ABSTRACT A multi-Gigahertz, low jitter phase locked loop (PLL) with adjustable gain is
disclosed. In one embodiment, properties of a fic signal of a PLL can be acquired. Properties …

(57) ABSTRACT A power-up detection circuit which operates in a stable way regardless of
variation in PVT. The power-up detection circuit includes a bias circuit that generates a bias …

Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage
detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the …

Various methods and devices that involve power-on-reset (POR) circuits are disclosed
herein. An exemplary POR circuit for generating a POR signal upon detecting that a supply …

The present invention provides a reset circuit which eliminates such conventional technical
defects and reduces a consumption current at the time of resetting. The present invention is …

A reference voltage generating circuit receives a power supply voltage and generates a
reference voltage. A reference voltage level guarantee circuit generates a sense signal …

Provided are a method and system for providing a power-on reset pulse. The system
includes a level detector configured to receive an input signal and produce, at least …

Externally configurable power-on-reset systems and methods for integrated circuits are
disclosed that utilize internal power-on-reset circuitry and reset control circuitry to provide …

(57) ABSTRACT A resetting device, of a separable extensive accessory, connected between
a portable device and an IC arranged in a separable extensive accessory. By using a simple …

FALTEST back to the normal high level, then determining whether or not the integrated
circuit has assumed the reset state. The testing can repeated with a plurality of lowerVCC …