Amber: Coarse-grained reconfigurable array-based soc for dense linear algebra acceleration

ALPACA: An Accelerator Chip for Nested Loop Programs

D Walter, M Brand, C Heidorn… - … on Circuits and …, 2024 - ieeexplore.ieee.org
ALPACA is an ASIC implementing an array of 8× 8 programmable processing elements for
accelerating nested loop programs. Each of them supports 32-bit as well as 8-bit floating …
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An Area-Efficient Coarse-Grained Reconfigurable Array Design for Approximate Computing

K Kutsuna, T Kojima, H Takase… - 2023 IEEE 16th …, 2023 - ieeexplore.ieee.org
There has recently been significant attention towards CGRAs (Coarse-Grained
Reconfigurable Arrays) due to their high processing performance, power savings, and …
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