This paper proposes a “quasi-synchronous” design approach for signal processing circuits,
in which timing violations are permitted, but without the need for a hardware compensation …

Recent studies on noisy decoding for LDPC codes rely on the assumption that the noise in
each component is independent and perpetual. This paper examines a noisy decoding …

A majority logic decoder made of unreliable logic gates, whose failures are transient and
data-dependent, is analyzed. Based on a combinatorial representation of fault …

Due to process variation in nanoscale manufacturing, there may be permanently missing
connections in information processing hardware. Due to timing errors in circuits, there may …

There are different types of error correction codes (CCE), each of which gives different trade-
offs interms of decoding performanceand energy consumption. We propose to deal with this …

Flash memory devices are increasingly being used in deep-space missions as on-board
data storage in spacecraft. The harsh environment these missions take place in involves …

In this paper, we perform a simulated fault injection reliability assessment of memory centric
flooded LDPC decoders affected by probabilistic storage errors. We investigate the error …

Information and coding-theoretic tools have had a significant impact on communications and
data storage systems. Recently, a number of works in this area have begun a study of …

Coding theory provides techniques which can ensure the error free transmission and
storage of data. This data is often used as input to various algorithms that run on hardware …

This dissertation studies problems of data management under unreliable conditions: how
can data be efficiently reconstructed, synchronized, transmitted, and stored in the presence …