Spell: Streaming parsing of system event logs

M Du, F Li - 2016 IEEE 16th International Conference on Data …, 2016 - ieeexplore.ieee.org
System event logs have been frequently used as a valuable resource in data-driven
approaches to enhance system health and stability. A typical procedure in system log …

[LIBRO][B] VLSI test principles and architectures: design for testability

LT Wang, CW Wu, X Wen - 2006 - books.google.com
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …

Non-deterministic exponential time has two-prover interactive protocols

L Babai, L Fortnow, C Lund - Computational complexity, 1991 - Springer
We determine the exact power of two-prover interactive proof systems introduced by Ben-Or,
Goldwasser, Kilian, and Wigderson (1988). In this system, two all-powerful …

[LIBRO][B] Delay fault testing for VLSI circuits

A Krstic, KTT Cheng - 1998 - books.google.com
With the ever-increasing speed of integrated circuits, violations of the performance
specifications are becoming a major factor affecting the product quality level. The need for …

Feedback set problems

P Festa, PM Pardalos, MG C. Resende - Encyclopedia of optimization, 2012 - Springer
In recent years (1990) feedback set problems have been the subject of growing interest.
They have found applications in many fields, including deadlock prevention [90], program …

[LIBRO][B] Digital logic testing and simulation

A Miczo - 2003 - books.google.com
Your road map for meeting today's digital testing challenges Today, digital logic devices are
common in products that impact public safety, including applications in transportation and …

ATPG for heat dissipation minimization during test application

S Wang, SK Gupta - Proceedings., International Test …, 1995 - ieeexplore.ieee.org
A new ATPG algorithm has been proposed that reduces average heat dissipation (between
successive test vectors) during test application. The objective is to permit safe and …

[PDF][PDF] An exact algorithm for selecting partial scan flip-flops

ST Chakradhar, A Balakrishnan… - Proceedings of the 31st …, 1994 - dl.acm.org
We develop an exact algorithm for selecting flip-flops in partial scan designs to break all
feedback cycles. The main ideas that allow us to solve this hard problem exactly for large …

[PDF][PDF] On determining scan flip-flops in partial-scan designs

DH Lee, SM Reddy - 1990 IEEE International Conference on …, 1990 - academia.edu
In this paper we report on procedures investigated to determine flip-flops to be scanned in
partial-scan designs for sequential circuits. The main idea pursued is to derive a minimal …

Timing-driven test point insertion for full-scan and partial-scan BIST

KT Cheng, CJ Lin - Proceedings of 1995 IEEE international test …, 1995 - ieeexplore.ieee.org
We propose timing-driven test point insertion methods for a full-scan based BIST scheme
and for a partial-scan based BIST scheme, where the global flip-flop cycles have been …