This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-
recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low …

This paper proposes a highly robust 16 transistor soft-error resilient SRAM cell (SERSC-
16T) to provide complete resilience to single event upsets (SEU). The proposed cell is …

With continuous advancement in technology, latches have become highly susceptible to
radiation induced soft-errors such as multi-node-upsets (MNU). To effectively resilient the …

This work proposes a high-performance 16-transistor radiation-hardened SRAM cell
(HP16T), which recovers from all single event upsets and from the internal node pair …

Technology scaling of integrated circuits into nanoscale feature sizes has decreased the
effectiveness of existing single-node-upset and double-node-upset hardening techniques in …

With the aggressive shrinking of transistor feature sizes, nano-scale CMOS circuits are
becoming more vulnerable to multi-node-upsets, eg, triple-node-upsets (TNUs) as well as …

With the aggressive scaling in the feature size of transistors, single-event triple-node-upsets
(TNUs) induced by charge sharing in CMOS circuits have become a significant reliability …

This paper proposes a double‐node upset complete resilient (DNUCR) latch to meet the
requirements of low orbit space applications for high robustness, cost‐effectiveness, and …

With the development of semiconductor technology, the shrinking of feature size in
integrated circuits has made them more sensitive to multiple-node-upsets (MNUs) …

Nonvolatile memories are widely used in emerging energy-harvesting Internet-of-Things
(IoT) applications, and nonvolatile memories constructed from FeFET devices hold great …