Comprehensive study of 1-bit full adder cells: review, performance comparison and scalability analysis

M Hasan, AH Siddique, AH Mondol, M Hossain… - SN Applied …, 2021 - Springer
Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units
(ALUs) of modern computing systems. Recently, there have been massive research interests …

1-Bit FinFET carry cells for low voltage high-speed digital signal processing applications

CS Pittala, V Vijay, BNK Reddy - Silicon, 2023 - Springer
In this paper, new high speed and low voltage 1-bit FinFET full adder carry cells are
proposed for multi-bit arithmetic applications used in Digital Signal Processing (DSP) …

A high-speed and scalable XOR-XNOR-based hybrid full adder design

M Hasan, MS Hussain, M Hossain, M Hasan… - Computers & Electrical …, 2021 - Elsevier
This work presents the design of a scalable and full-swing Full Adder (FA) based on the
XOR-XNOR module. The performance of the design has been compared with eleven …

Quantum‐Dot Cellular Automata‐Based Full Adder Design: Comprehensive Review and Performance Comparison

UB Joy, S Chakraborty, S Islam… - … in Materials Science …, 2023 - Wiley Online Library
Being one of the promising techniques for future computing systems, quantum‐dot cellular
automata (QCA)‐based circuit design has gained massive interest among researchers due …

A high‐performance full swing 1‐bit hybrid full adder cell

S Hussain, M Hasan, G Agrawal… - IET Circuits, Devices & …, 2022 - Wiley Online Library
This study proposes an 18‐transistor full adder (FA) cell based on the full swing hybrid logic
style. It has a first stage comprising the XOR‐XNOR module followed by pass transistors and …

Design of a two-bit magnitude comparator based on pass transistor, transmission gate and conventional static CMOS logic

S Lubaba, KM Faisal, MS Islam… - 2020 11th International …, 2020 - ieeexplore.ieee.org
Since there is a swift technological progress going on in the recent years, semiconductor
industry evolved to such an extend that requirement of optimal performance in electronic …

A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder

M Hasan, MS Hossain, AH Siddique, M Hossain… - Microelectronics …, 2021 - Elsevier
Abstract A 4-bit Carry Look-Ahead (CLA) architecture for carry-generation process is
proposed. CLA architecture proposed in this work uses complex CLA circuits for carry …

Tolerant and low power subtractor with 4: 2 compressor and a new TG‐PTL‐float full adder cell

A Sadeghi, N Shiri, M Rafiee… - IET Circuits, Devices & …, 2022 - Wiley Online Library
A new 1‐bit full adder (FA) cell illustrating low‐power, high‐speed, and a small area is
presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float …

Healthcare monitoring system for dedicated COVID-19 hospitals or isolation centers

JN Chanda, IA Chowdhury, M Peyaru… - 2021 IEEE Mysore …, 2021 - ieeexplore.ieee.org
Remote monitoring of patients can help reduce the health risks of doctors and nurses in
dedicated COVID-19 hospitals or isolation units. The physiological data such as body …

An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending

A Sadeghi, N Shiri, M Rafiee, M Tahghigh - Frontiers of Information …, 2022 - Springer
We present a new counter-based Wallace-tree (CBW) 8× 8 multiplier. The multiplier's
counters are implemented with a new hybrid full adder (FA) cell, which is based on the …