A 135-155 GHz 9.7%/16.6% DC-RF/DC-EIRP efficiency frequency multiply-by-9 FMCW transmitter...

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An overview of state-of-the-art D-band radar system components

P Stadler, H Papurcu, T Welling, S Tejero Alfageme… - Chips, 2022 - mdpi.com
In this article, a literature study has been conducted including 398 radar circuit elements
from 311 recent publications (mostly between 2010 and 2022) that have been reported …
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A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS

S Park, DW Park, K Vaesen… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This article presents a 135–155-GHz low-power and high-efficiency frequency multiply-by-9
(x9) frequency-modulated continuous-wave (FMCW) radar transmitter (TX). Starting from a …
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A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS

A Kankuppe, S Park, K Vaesen… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
A 139.5–157.7-GHz-band I/Q radar receiver with an on-chip antenna and a spillover resilient-
path baseband filter is presented. Spillover and its manifestation based on the chirp duration …
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A compact D-band CMOS frequency sixtupler using a mode analysis of the harmonics

DJ Shin, UG Choi, JR Yang - IEEE Transactions on Microwave …, 2022 - ieeexplore.ieee.org
A miniaturized D-band frequency sixtupler using a mode analysis of the harmonics is
proposed to improve the output power of the CMOS process using a low driving signal. The …
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A 5.1 dBm 127–162 GHz frequency sextupler with broadband compensated transformer-based baluns in 22nm FD-SOI CMOS

S Li, W Chen, X Li, Y Wang - 2022 IEEE Radio Frequency …, 2022 - ieeexplore.ieee.org
This paper presents a D-band frequency sextupler in 22 nm FD-SOI CMOS. It consists of a
differential frequency tripler followed by a push-push frequency doubler for six times …
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Design and Analysis of Complex Neutralization Gain-Boosting Technique With Low-Loss Power Combining for Efficient, Linear D-Band Power Amplifiers

M Eleraky, TY Huang, Y Liu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This article introduces a comprehensive design and optimization approach aimed at
significantly improving the power gain of a given device to achieve the theoretical maximum …
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A 195–244 GHz CMOS self-mixing frequency tripler with> 23 dBc fundamental rejection

Z Lin, Y Shen, Y Ding, J Zou, S Hu - AEU-International Journal of …, 2024 - Elsevier
This paper presents a wideband and high-fundamental rejection self-mixing frequency
tripler in a 40-nm CMOS. The proposed tripler consists of an input half-shielded transformer …
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Analysis and Design of Broadband Balance-Compensated Transformer Baluns for Silicon-Based Millimeter-Wave Circuits

S Li, B **a, X Li, Y Wang, X Liu… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
This paper presents the analysis and design of broadband balance-compensated
transformer baluns, suitable for silicon-based millimeter-wave (mm-wave) circuits requiring …
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32.1 dB Gain D-Band Line-Based Power Amplifier for 5G-Advanced Applications in 22nm FDSOI Technology

JD Cañeda, JA Hora, X Zhu - 2024 23rd International …, 2024 - ieeexplore.ieee.org
This paper presents a design of a D-band transmission line-based power amplifier (LB-PA)
which employed a pseudo-differential topology technique and utilizes the Coupled Slow …
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A D-Band 28nm CMOS-Bulk Power Amplifier with 12.8 dBm Output Power and 31.3 GHz 3dB Bandwidth

P Stadler, H Papurcu, J Romstadt… - 2024 IEEE 24th Topical …, 2024 - ieeexplore.ieee.org
We present a 2-way, 4-stage power amplifier (PA) in TSMC's 28nm CMOS-bulk technology.
The D-Band PA consists of three capacitively-neutralized, common-source (CS) gain stages …
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