ABCDPlace: Accelerated batch-based concurrent detailed placement on multithreaded CPUs and GPUs

Y Lin, W Li, J Gu, H Ren, B Khailany… - IEEE transactions on …, 2020 - ieeexplore.ieee.org
Placement is an important step in modern verylarge-scale integrated (VLSI) designs.
Detailed placement is a placement refining procedure intensively called throughout the …

Mixed-cell-height legalization considering technology and region constraints

Z Zhu, J Chen, W Zhu, YW Chang - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Mixed-cell-height circuits have become popular in advanced technologies for better power,
area, routability, and performance tradeoffs. With technology and region constraints imposed …

Mixed-cell-height detailed placement considering complex minimum-implant-area constraints

J Chen, YW Chang, YY Wu - IEEE Transactions on Computer …, 2020 - ieeexplore.ieee.org
Mixed-cell-height circuits have prevailed in advanced technology to address various design
requirements. Along with device scaling, complex minimum-implant-area (MIA) constraints …

A robust modulus-based matrix splitting iteration method for mixed-cell-height circuit legalization

J Chen, Z Zhu, W Zhu, C Yao-Wen - ACM Transactions on Design …, 2020 - dl.acm.org
Modern circuits often contain standard cells of different row heights to meet various design
requirements. Taller cells give larger drive strengths and higher speed at the cost of larger …

A row-based algorithm for non-integer multiple-cell-height placement

ZY Lin, YW Chang - 2021 IEEE/ACM International Conference …, 2021 - ieeexplore.ieee.org
A circuit design with non-integer multiple cell height (NIMCH) is more flexible for optimizing
area, timing, and power simultaneously. A cell with a larger height provides higher pin …

Integrating operations research into very large-scale integrated circuits placement design: A review

B Zhang, L Zhen, S Wang, F Yang - Asia-Pacific Journal of …, 2024 - ideas.repec.org
The placement stage of the physical design of very large-scale integrated circuits (VLSI)
specifies the arrangement and order of standard cells and devices within an area, and the …

Mixed-cell-height placement with drain-to-drain abutment and region constraints

J Chen, Z Zhu, L Guo, YW Tseng… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Along with device scaling, the drain-to-drain abutment (DDA) and fence region constraints
arise as emerging challenges in modern circuit designs, incurring additional difficulties …

Two Variants of Robust Two-Step Modulus-Based Matrix Splitting Iteration Methods for Mixed-Cell-Height Circuit Legalization Problem

LX Wang, Y Cao, QQ Shen - Communications on Applied Mathematics and …, 2024 - Springer
The mathematical formulation of the mixed-cell-height circuit legalization (MCHCL) problem
can be expressed by a linear complementarity problem (LCP) with the system matrix being a …

MIA-aware detailed placement and VT reassignment for leakage power optimization

HC Lin, SY Fang - Proceedings of the 28th Asia and South Pacific …, 2023 - dl.acm.org
As the feature size decreases, leakage power consumption becomes an important target in
the design. Using multiple threshold voltages (VTs) in cell-based designs is a popular …

Mixed-cell-height legalization considering complex minimum width constraints and half-row fragmentation effect

Z Zhu, Z Huang, P Yang, W Zhu, J Chen, H Zhou… - Integration, 2020 - Elsevier
With the increasing complexity in modern circuit designs, the 6T&6TPPNN circuits have
become popular in advanced technologies for better trade-offs among routability, timing …