[HTML][HTML] Energy digital twin technology for industrial energy management: Classification, challenges and future

W Yu, P Patros, B Young, E Klinac… - … and Sustainable Energy …, 2022 - Elsevier
Digitalisation of the process and energy industries through energy digital twin technology
promises step-improvements in energy management and optimisation, better servicing and …

[HTML][HTML] Modern computing: Vision and challenges

SS Gill, H Wu, P Patros, C Ottaviani, P Arora… - … and Informatics Reports, 2024 - Elsevier
Over the past six decades, the computing systems field has experienced significant
transformations, profoundly impacting society with transformational developments, such as …

FPGA architecture: Principles and progression

A Boutros, V Betz - IEEE Circuits and Systems Magazine, 2021 - ieeexplore.ieee.org
Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs)
have been widely used to implement a myriad of applications from different domains. As a …

Programming and synthesis for software-defined FPGA acceleration: status and future prospects

YH Lai, E Ustun, S **ang, Z Fang, H Rong… - ACM Transactions on …, 2021 - dl.acm.org
FPGA-based accelerators are increasingly popular across a broad range of applications,
because they offer massive parallelism, high energy efficiency, and great flexibility for …

Exploring eFPGA-based redaction for IP protection

J Bhandari, AKT Moosa, B Tan, C Pilato… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
Recently, eFPGA-based redaction has been proposed as a promising solution for hiding
parts of a digital design from untrusted entities, where legitimate end-users can restore …

RLPlace: Using reinforcement learning and smart perturbations to optimize FPGA placement

MA Elgammal, KE Murray, V Betz - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Simulated annealing (SA) is one of the most common FPGA placement techniques, and is
used both as a standalone algorithm and to improve an initial analytical placement. While …

Koios: A deep learning benchmark suite for FPGA architecture and CAD research

A Arora, A Boutros, D Rauch, A Rajen… - … Conference on Field …, 2021 - ieeexplore.ieee.org
With the prevalence of deep learning (DL) in many applications, researchers are
investigating different ways of optimizing FPGA architecture and CAD to achieve better …

SymbiFlow and VPR: An open-source design flow for commercial and novel FPGAs

KE Murray, MA Elgammal, V Betz, T Ansell… - IEEE Micro, 2020 - ieeexplore.ieee.org
As the benefits of Moore's Law diminish, computing performance, and efficiency gains are
increasingly achieved through specializing hardware to a domain of computation. However …

AIR: A fast but lazy timing-driven FPGA router

KE Murray, S Zhong, V Betz - 2020 25th Asia and South Pacific …, 2020 - ieeexplore.ieee.org
Routing is a key step in the FPGA design process, which significantly impacts design
implementation quality. Routing is also very time-consuming, and can scale poorly to very …

Overview of prospects for service-aware radio access towards 6G networks

Z Zhao, Q Du, D Wang, X Tang, H Song - Electronics, 2022 - mdpi.com
The integration of space–air–ground–sea networking in 6G, which is expected to not only
achieve seamless coverage but also offer service-aware access and transmission, has …