Timing closure is the most critical phase of modern system-on-chip implementation: without
timing closure, there is no tapeout. Timing closure is the end result of (i) years of …

Meeting clock skew constraint is one of the most important tasks in the synthesis of clock
trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals …

In the clock network design, the trade-off between power consumption and timing closure is
an important and difficult issue. The clock tree architecture has a shorter wire length and …

Instead of minimizing clock skew, skew can be useful to improve circuit performance.
However, it is difficult to apply useful skew to a design with complicated power modes. With …

In this article, a fully digital system to detect and correct setup/hold time violations in digital
circuits, is presented. The proposed system benefits from simple, low-power, small-area, and …

Satisfying a clock skew constraint is one of the most important tasks in clock tree synthesis.
Moreover, the task becomes much harder to solve when the clock tree is designed in a …

This paper proposes a graph-based algorithm for solving the adjustable delay buffer (ADB)
allocation problem optimally under useful clock skew scheduling. Our algorithm supports …

The clock buffer polarity assignment is one of the effective design schemes to mitigate the
power/ground noise caused by the clock signal propagation in high-speed digital systems …

Power consumption is known to be a crucial issue in current IC designs. To tackle this
problem, Multiple Dynamic Supply Voltage (MDSV) designs are proposed as an efficient …

The problem of meeting the skew constraint in clock trees becomes much hard as the IC
design paradigm has been shifting to multiple power supply mode design, in which the clock …