As silicon technology enters sub-20nm nodes, new materials, structures and processes are
being introduced in order to continue with the advantages of dimensional scaling, eg, 3D …

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO 2 based
devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and …

The key message of this paper is that process variation is not an insurmountable barrier to
Moore's Law, but is simply another challenge to be overcome. This message is illustrated …

It has been demonstrated that the introduction of HfO 2/TiN gate stacks into CMOS
technologies provides the means to continue with traditional device gate length scaling …

This paper reviews the topic of the device parameter variations using semiconductor-based
manufacturing of micro-and nano-devices. There is considerable misunderstanding about …

2. Description of the Related Art Strained silicon is being used by the semiconductor indus
try to improve transistor performance. Increased Strain levels are desired in future …

Ultra-low voltage operation is key to achieving energy-efficient operation for microcontroller
(MCU) systems. Variation resiliency, high speed operation, and short design time are the …

High-k dielectrics have been intensively investigated during the last decade, and their
performance as a gate dielectric has been improved to the level of conventional SiO 2 …

The introduction of novel gate stack materials (high-k/metal gate) has enabled the
resumption of Moore's Law at the 45/32nm nodes, when conventional Poly/SiON gate stacks …

A 3-D TCAD framework is proposed for simulating Negative Bias Temperature Instability
(NBTI) in Silicon (Si) and Silicon Germanium (SiGe) channel p-MOSFETs. Different types of …