VPR: A new packing, placement and routing tool for FPGA research

V Betz, J Rose - International Workshop on Field Programmable Logic …, 1997 - Springer
We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile
Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published …

[KNIHA][B] Architecture and CAD for deep-submicron FPGAs

V Betz, J Rose, A Marquardt - 2012 - books.google.com
Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become
one of the most popular implementation media for digital circuits and have grown into a $2 …

[KNIHA][B] Three-dimensional integrated circuit design

VF Pavlidis, I Savidis, EG Friedman - 2017 - books.google.com
Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more
than twice as much new content, adding the latest developments in circuit models …

Architectures and algorithms for field-programmable gate arrays with embedded memory

SJE Wilton - 1997 - utoronto.scholaris.ca
Recent dramatic improvements in integrated circuit fabrication technology have led to Field-
Programmable Gate Arrays (FPGAs) capable of implementing entire digital systems, as …

A comparative study of two Boolean formulations of FPGA detailed routing constraints

GJ Nam, F Aloul, K Sakallah, R Rutenbar - Proceedings of the 2001 …, 2001 - dl.acm.org
A Boolean-based router expresses the routing constraints as a Bool? ean function which is
satisfiable if and only if the layout is routable. Compared to traditional routers, Boolean …

[PDF][PDF] New performance-driven FPGA routing algorithms

MJ Alexander, G Robins - Proceedings of the 32nd annual ACM/IEEE …, 1995 - dl.acm.org
Motivated by the goal of increasing the performance of FPGA-based designs, we propose e
ective Steiner and arborescence FPGA routing algorithms. Our graphbased Steiner tree …

[PDF][PDF] Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based boolean SAT

GJ Nam, KA Sakallah, RA Rutenbar - … of the 1999 ACM/SIGDA seventh …, 1999 - dl.acm.org
Field-Programmable Gate Arrays (FPGAs) have adopted and successfully adapted a variety
of ASIC layout techniques. Iterative improvement placers [4], maze-style[191 and channel …

Design methodology of a low-energy reconfigurable single-chip DSP system

M Wan, H Zhang, V George, M Benes… - Journal of VLSI signal …, 2001 - Springer
In this paper, we first present a reconfigurable architecture template for low-power digital
signal processing, and then an energy conscious design methodology to bridge the …

Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs

H Zhang, M Wan, V George… - … . IEEE Computer Society …, 1999 - ieeexplore.ieee.org
In this paper we present and analyze a number of interconnect architectures for
reconfigurable systems targeting applications in the areas of wireless communication and …

Placement and Routing for Performance‐Oriented FPGA Layout

MJ Alexander, JP Cohoon, JL Ganley, G Robins - VLSI Design, 1998 - Wiley Online Library
This paper presents a performance‐oriented placement and routing tool for field‐
programmable gate arrays. Using recursive geometric partitioning for simultaneous …