The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory

L Subramanian, V Seshadri, A Ghosh, S Khan… - Proceedings of the 48th …, 2015 - dl.acm.org
In a multi-core system, interference at shared resources (such as caches and main memory)
slows down applications running on different cores. Accurately estimating the slowdown of …

Reducing memory interference in multicore systems via application-aware memory channel partitioning

SP Muralidhara, L Subramanian, O Mutlu… - Proceedings of the 44th …, 2011 - dl.acm.org
Main memory is a major shared resource among cores in a multicore system. If the
interference between different applications' memory requests is not controlled effectively …

Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems

R Ausavarungnirun, KKW Chang… - ACM SIGARCH …, 2012 - dl.acm.org
When multiple processor (CPU) cores and a GPU integrated together on the same chip
share the off-chip main memory, requests from the GPU can heavily interfere with requests …

[PDF][PDF] Usimm: the utah simulated memory module

N Chatterjee, R Balasubramonian, M Shevgoor… - University of Utah, Tech …, 2012 - Citeseer
Abstract USIMM, the Utah SImulated Memory Module, is a DRAM main memory system
simulator that is being released for use in the Memory Scheduling Championship (MSC) …

FLIN: Enabling fairness and enhancing performance in modern NVMe solid state drives

A Tavakkol, M Sadrosadati, S Ghose… - 2018 ACM/IEEE 45th …, 2018 - ieeexplore.ieee.org
Modern solid-state drives (SSDs) use new host-interface protocols, such as NVMe, to
provide applications with fast access to storage. These new protocols make use of a concept …

Utility-based hybrid memory management

Y Li, S Ghose, J Choi, J Sun, H Wang… - … Conference on Cluster …, 2017 - ieeexplore.ieee.org
While the memory footprints of cloud and HPC applications continue to increase,
fundamental issues with DRAM scaling are likely to prevent traditional main memory …

Mask: Redesigning the gpu memory hierarchy to support multi-application concurrency

R Ausavarungnirun, V Miller, J Landgraf… - ACM SIGPLAN …, 2018 - dl.acm.org
Graphics Processing Units (GPUs) exploit large amounts of threadlevel parallelism to
provide high instruction throughput and to efficiently hide long-latency stalls. The resulting …

DASH: Deadline-aware high-performance memory scheduler for heterogeneous systems with hardware accelerators

H Usui, L Subramanian, KKW Chang… - ACM Transactions on …, 2016 - dl.acm.org
Modern SoCs integrate multiple CPU cores and hardware accelerators (HWAs) that share
the same main memory system, causing interference among memory requests from different …

FIRM: Fair and high-performance memory control for persistent memory systems

J Zhao, O Mutlu, Y **e - 2014 47th Annual IEEE/ACM …, 2014 - ieeexplore.ieee.org
Byte-addressable nonvolatile memories promise a new technology, persistent memory,
which incorporates desirable attributes from both traditional main memory (byte …

The blacklisting memory scheduler: Achieving high performance and fairness at low cost

L Subramanian, D Lee, V Seshadri… - 2014 IEEE 32nd …, 2014 - ieeexplore.ieee.org
In a multicore system, applications running on different cores interfere at main memory. This
inter-application interference degrades overall system performance and unfairly slows down …