Enabling resource-efficient aiot system with cross-level optimization: A survey
The emerging field of artificial intelligence of things (AIoT, AI+ IoT) is driven by the
widespread use of intelligent infrastructures and the impressive success of deep learning …
widespread use of intelligent infrastructures and the impressive success of deep learning …
Dynamic vision sensor integration on fpga-based cnn accelerators for high-speed visual classification
Deep-learning is a cutting edge theory that is being applied to many fields. For vision
applications the Convolutional Neural Networks (CNN) are demanding significant accuracy …
applications the Convolutional Neural Networks (CNN) are demanding significant accuracy …
Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC
Abstract The Two-Dimensional Fast Fourier Transform (2D-FFT) algorithm is used for the
study of many modern systems applied for security and biometrics. The adoption of this …
study of many modern systems applied for security and biometrics. The adoption of this …
Optimizing a Field-Programmable Gate Array Object Detection System Considering Processing System and Programmable Logic Load Balance
Y Watanabe, H Tamukoh - … of Robotics, Networking and Artificial Life, 2023 - jstage.jst.go.jp
ABSTRACT A field-programmable gate array (FPGA) device with a Zynq architecture
integrates a processing system (PS) and programmable logic (PL) into a single chip …
integrates a processing system (PS) and programmable logic (PL) into a single chip …
[PDF][PDF] Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC
The Two-Dimensional Fast Fourier Transform (2D-FFT) algorithm is used for the study of
many modern systems applied for security and biometrics. The adoption of this algorithm …
many modern systems applied for security and biometrics. The adoption of this algorithm …
Synchronization of axi streaming interfaces for convolution core implementation on fpga
T Sledevič - 2019 IEEE 7th IEEE Workshop on Advances in …, 2019 - ieeexplore.ieee.org
The article presents application of DMA controllers in conjunction with ZynQ SoC high
performance ports for data streaming to convolution core implemented on programmable …
performance ports for data streaming to convolution core implemented on programmable …
A Multi-Memory Field-Programmable Custom Computing Machine for Accelerating Compute-Intensive Applications
In this paper, we present an FPGA-based multi-memory controller for accelerating
computationally intensive applications. Our architecture accepts multiple inputs and …
computationally intensive applications. Our architecture accepts multiple inputs and …
Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems
The use of accelerator-centric processing architectures in different application scenarios,
ranging from the cloud to the edge, is nowadays a reality. However, the always increasing …
ranging from the cloud to the edge, is nowadays a reality. However, the always increasing …
Unified address space for multiple hardware accelerators using dedicated low latency links
S Singh, HC Neema, S Santan, KK Dao… - US Patent …, 2020 - Google Patents
A system may include a host processor coupled to a communication bus, a first hardware
accelerator communicatively linked to the host processor through the communication bus …
accelerator communicatively linked to the host processor through the communication bus …
[PDF][PDF] Подход к проектированию динамически реконфигурируемых блоков арбитража для встраиваемых систем
ЕА Суворова - Радиопромышленность, 2019 - scholar.archive.org
В настоящее время активно развивается направление разработки динамически
реконфигурируемых компонентов для встраиваемых систем на базе FPGA. Однако …
реконфигурируемых компонентов для встраиваемых систем на базе FPGA. Однако …