Engineering metallic nanostructures for plasmonics and nanophotonics

NC Lindquist, P Nagpal, KM McPeak… - Reports on Progress …, 2012 - iopscience.iop.org
Metallic nanostructures now play an important role in many applications. In particular, for the
emerging fields of plasmonics and nanophotonics, the ability to engineer metals on …

Silicon nanowires for photovoltaic solar energy conversion

KQ Peng, ST Lee - Advanced Materials, 2011 - Wiley Online Library
Semiconductor nanowires are attracting intense interest as a promising material for solar
energy conversion for the new‐generation photovoltaic (PV) technology. In particular, silicon …

Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension

S Pi, C Li, H Jiang, W **a, H **n, JJ Yang… - Nature nanotechnology, 2019 - nature.com
The memristor, is a promising building block for next-generation non-volatile memory,
artificial neural networks,,–and bio-inspired computing systems,. Organizing small …

Tri-gate devices and methods of fabrication

RS Chau, BS Doyle, J Kavalieros, D Barlage… - US Patent …, 2008 - Google Patents
4,906,589 A 3, 1990 Chao 4,996,574 A 2f1991 Shirasaki et al. 5,124,777 A 6, 1992 Lee
5,338,959 A 8, 1994 Kim et al. 5,346,839 A 9, 1994 Sundaresan................. 438/164 …

Method of forming a metal oxide dielectric

JK Brask, BS Doyle, J Kavalleros, M Doczy… - US Patent …, 2008 - Google Patents
(57) ABSTRACT A semiconductor device comprising a semiconductor body having a top
surface and a first and second laterally opposite sidewalls as formed on an insulating …

Nonplanar transistors with metal gate electrodes

JK Brask, BS Doyle, ML Doczy, RS Chau - US Patent 7,105,390, 2006 - Google Patents
(57) ABSTRACT A semiconductor device comprising a semiconductor body having a top
Surface and a first and second laterally opposite sidewalls as formed on an insulating …

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

SA Hareland, RS Chau, BS Doyle, R Rios… - US Patent …, 2010 - Google Patents
US PATENT DOCUMENTS 6,163,053 A 12/2000 Kawashima 6,165,880 A 12/2000 Yaung
et al. 5, 120,666 A 6, 1992 Gotou........................ 438/164 6,174,820 B1 1/2001 Habermehl et …

Turning silicon on its edge [double gate CMOS/FinFET technology]

EJ Nowak, I Aller, T Ludwig, K Kim… - IEEE Circuits and …, 2004 - ieeexplore.ieee.org
Double-gate devices will enable the continuation of CMOS scaling after conventional
scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate …

Metal silicides in CMOS technology: Past, present, and future trends

SL Zhang, M Östling - Critical Reviews in Solid State and Materials …, 2003 - Taylor & Francis
Metal silicides have played an indispensable role in the raped development of
microelectronics since PtSi was first used to improve the rectifying characteristics of diodes …

Recent progress in simple and cost‐effective top‐down lithography for≈ 10 nm scale nanopatterns: from edge lithography to secondary sputtering lithography

WB Jung, S Jang, SY Cho, HJ Jeon… - Advanced …, 2020 - Wiley Online Library
The development of a simple and cost‐effective method for fabricating≈ 10 nm scale
nanopatterns over large areas is an important issue, owing to the performance …