An industrial view of electronic design automation
The automation of the design of electronic systems and circuits [electronic design
automation (EDA)] has a history of strong innovation. The EDA business has profoundly …
automation (EDA)] has a history of strong innovation. The EDA business has profoundly …
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
High-throughput and area-efficient designs of hash functions and corresponding
mechanisms for Message Authentication Codes (MACs) are in high demand due to new …
mechanisms for Message Authentication Codes (MACs) are in high demand due to new …
Design of high speed carry save adder using carry lookahead adder
RA Javali, RJ Nayak, AM Mhetar… - International …, 2014 - ieeexplore.ieee.org
Addition is one of the essential operations in Digital Signal Processing (DSP) applications
which includes Fast Fourier Transform (FFT), Digital filters, multipliers etc. With the …
which includes Fast Fourier Transform (FFT), Digital filters, multipliers etc. With the …
A top-down design methodology for ultrahigh-performance hashing cores
Many cryptographic primitives that are used in cryptographic schemes and security protocols
such as SET, PKI, IPSec, and VPNs utilize hash functions, which form a special family of …
such as SET, PKI, IPSec, and VPNs utilize hash functions, which form a special family of …
Enhancing mergeability of datapaths and reducing datapath widths responsively to required precision
S Saluja, A Mathur - US Patent 6,772,399, 2004 - Google Patents
A practical definition for determining a required precision is provided and used to reduce the
widths of operators and edges of data flow graphs. A bottom-up procedure for systematically …
widths of operators and edges of data flow graphs. A bottom-up procedure for systematically …
Optimising the SHA‐512 cryptographic hash function on FPGAs
GS Athanasiou, HE Michail… - IET Computers & …, 2014 - Wiley Online Library
In this study, novel pipelined architectures, optimised in terms of throughput and
throughput/area factors, for the SHA‐512 cryptographic hash function, are proposed. To …
throughput/area factors, for the SHA‐512 cryptographic hash function, are proposed. To …
A power-efficient implementation of sha-256 hash function for embedded applications
SHA-256 is a well-known algorithm widely used in many security applications. The algorithm
provides a sufficient level of safety and can be performed efficiently by FPGA devices due to …
provides a sufficient level of safety and can be performed efficiently by FPGA devices due to …
PV-MAC: Multiply-and-accumulate unit structure exploiting precision variability in on-device convolutional neural networks
J Kang, T Kim - Integration, 2020 - Elsevier
The work proposes a new multiply-and-accumulate (MAC) processing unit structure that is
highly suitable for on-device convolutional neural networks (CNNs). By observing that the bit …
highly suitable for on-device convolutional neural networks (CNNs). By observing that the bit …
High performance complex number multiplier using booth-wallace algorithm
This paper presents the methods required to implement a high speed and high performance
parallel complex number multiplier. The designs are structured using Radix-4 Modified …
parallel complex number multiplier. The designs are structured using Radix-4 Modified …
Optimizing high speed arithmetic circuits using three-term extraction
A Hosangadi, F Fallah, R Kastner - Proceedings of the Design …, 2006 - ieeexplore.ieee.org
Carry save adder (CSA) trees are commonly used for high speed implementation of multi-
operand additions. We present a method to reduce the number of the adders in CSA trees …
operand additions. We present a method to reduce the number of the adders in CSA trees …