With the increasing demand for SoCs to include rich functionality, SoCs are being designed
with hundreds of small memories with different sizes and frequencies. If memory BIST logics …

This paper presents a reconfigurable built-in self-repair (ReBISR) scheme for multiple
repairable RAM cores with different sizes and redundancy organizations (ie, spare …

We propose a structured design methodology to construct FSM-based programmable
memory BIST. The proposed BIST can be programmed on-line, with a" macro command", to …

A system-on-chip (SOC) usually consists of many memory cores with different sizes and
functionality, and they typically represent a significant portion of the SOC and therefore …

This paper describes a hardware/software strategy for the effective and efficient
management of several distributed Memory Built-In Self-Test (MBIST) units orchestrated by a …

Memory testing is becoming the dominant factor in testing a system-on-chip (SoC), with the
rapid growth of the size and density of embedded memories. To minimize the test effort, we …

Two of the most commonly used models in computational learning theory are the distribution-
free model, in which examples are chosen from a fixed but arbitrary distribution, and the …

The test scheduling of memory cores can significantly affect the test time and power of
system chips. We propose a test scheduling algorithm for BISTed memory cores to minimize …

Testing and diagnosis are important issues in system-on-chip (SoC) development, as more
and more embedded cores are being integrated into the chips. In this paper we propose a …

Due to the pin-count limitation, built-in self-diagnosis (BISD) for embedded RAMs usually
exports diagnosis information serially, which results in the overhead of diagnostic time. This …