Programming and synthesis for software-defined FPGA acceleration: status and future prospects
FPGA-based accelerators are increasingly popular across a broad range of applications,
because they offer massive parallelism, high energy efficiency, and great flexibility for …
because they offer massive parallelism, high energy efficiency, and great flexibility for …
ThunderGP: HLS-based graph processing framework on FPGAs
FPGA has been an emerging computing infrastructure in datacenters benefiting from
features of fine-grained parallelism, energy efficiency, and reconfigurability. Meanwhile …
features of fine-grained parallelism, energy efficiency, and reconfigurability. Meanwhile …
AutoDSE: Enabling software programmers to design efficient FPGA accelerators
Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized
computing, but the fact that FPGAs are hard to program creates a steep learning curve for …
computing, but the fact that FPGAs are hard to program creates a steep learning curve for …
HeteroCL: A multi-paradigm programming infrastructure for software-defined reconfigurable computing
With the pursuit of improving compute performance under strict power constraints, there is
an increasing need for deploying applications to heterogeneous hardware architectures with …
an increasing need for deploying applications to heterogeneous hardware architectures with …
Towards a comprehensive benchmark for high-level synthesis targeted to FPGAs
High-level synthesis (HLS) aims to raise the abstraction layer in hardware design, enabling
the design of domain-specific accelerators (DSAs) like field-programmable gate arrays …
the design of domain-specific accelerators (DSAs) like field-programmable gate arrays …
Extending high-level synthesis for task-parallel programs
C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-
programmable gate array (FPGA) accelerators in many application domains in recent years …
programmable gate array (FPGA) accelerators in many application domains in recent years …
SuSy: A programming model for productive construction of high-performance systolic arrays on FPGAs
Systolic algorithms are one of the killer applications on spatial architectures such as FPGAs
and CGRAs. However, it requires a tremendous amount of human effort to design and …
and CGRAs. However, it requires a tremendous amount of human effort to design and …
Democratizing domain-specific computing
Democratizing Domain-Specific Computing Page 1 GENERAL-PURPOSE COMPUTERS
ARE widely used in our modern society. There were close to 24 million software …
ARE widely used in our modern society. There were close to 24 million software …
Data-driven offline optimization for architecting hardware accelerators
Industry has gradually moved towards application-specific hardware accelerators in order to
attain higher efficiency. While such a paradigm shift is already starting to show promising …
attain higher efficiency. While such a paradigm shift is already starting to show promising …
Performance modeling and directives optimization for high-level synthesis on FPGA
High-level synthesis (HLS) relies on the use of synthesis directives to generate digital
designs meeting a set of specifications. However, the selection of directives depends largely …
designs meeting a set of specifications. However, the selection of directives depends largely …