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Multi-core devices for safety-critical systems: A survey
Multi-core devices are envisioned to support the development of next-generation safety-
critical systems, enabling the on-chip integration of functions of different criticality. This …
critical systems, enabling the on-chip integration of functions of different criticality. This …
GPU devices for safety-critical systems: A survey
Graphics Processing Unit (GPU) devices and their associated software programming
languages and frameworks can deliver the computing performance required to facilitate the …
languages and frameworks can deliver the computing performance required to facilitate the …
A survey of energy-aware scheduling in mixed-criticality systems
YW Zhang, RK Chen - Journal of Systems Architecture, 2022 - Elsevier
Unlike traditional embedded systems only have one criticality level, mixed-criticality (MC)
systems integrate different types of applications or functionalities into a common and shared …
systems integrate different types of applications or functionalities into a common and shared …
Energy aware fixed priority scheduling in mixed-criticality systems
YW Zhang, RK Chen - Computer Standards & Interfaces, 2023 - Elsevier
Most of studies about energy management for MC systems are based on dynamic priority
scheme. The disadvantages of dynamic priority scheme are high system overhead and poor …
scheme. The disadvantages of dynamic priority scheme are high system overhead and poor …
Towards mixed criticality task scheduling in cyber physical systems: Challenges and perspectives
Cyber physical systems (CPSs) are a fast-evolving technology based on a strong synergy
between heterogeneous sensing, networking, computation and control modules. When …
between heterogeneous sensing, networking, computation and control modules. When …
Energy-aware mixed-criticality sporadic task scheduling algorithm
YW Zhang - IEEE Transactions on Computer-Aided Design of …, 2020 - ieeexplore.ieee.org
The mixed-criticality system provides multiple real-time applications with different criticalities
in a single system. Poor energy-saving performance of the previous studies on mixed …
in a single system. Poor energy-saving performance of the previous studies on mixed …
A hypervisor architecture for low-power real-time embedded systems
T Poggi, P Onaindia… - 2018 21st Euromicro …, 2018 - ieeexplore.ieee.org
This paper presents a hypervisor architecture tailored to low-power real-time applications.
This architecture extends the capability of a hypervisor by providing power management …
This architecture extends the capability of a hypervisor by providing power management …
Safety and security concept for software updates on mixed-criticality systems
The raising connectivity of critical embedded systems makes them vulnerable to cyber-
security attacks that compromise not only privacy but also safety. This results in intricate …
security attacks that compromise not only privacy but also safety. This results in intricate …
Detection and Localization of Hardware-Assisted Intermittent Power Attacks in Mixed-Critical Systems
Increasing complexity in power management (PMT) has led to a growing demand for third-
party power managers (3PPMs) in Network-on-Chip based Mixed-Critical Systems …
party power managers (3PPMs) in Network-on-Chip based Mixed-Critical Systems …
[HTML][HTML] Experimental evaluation of SAFEPOWER architecture for safe and power-efficient mixed-criticality systems
M Fakih, K Grüttner, S Schreiner, R Seyyedi… - Journal of Low Power …, 2019 - mdpi.com
With the ever-increasing industrial demand for bigger, faster and more efficient systems, a
growing number of cores is integrated on a single chip. Additionally, their performance is …
growing number of cores is integrated on a single chip. Additionally, their performance is …