A review on compact modeling of multiple-gate MOSFETs

J Song, B Yu, Y Yuan, Y Taur - IEEE Transactions on Circuits …, 2009 - ieeexplore.ieee.org
This paper reviews recent development on compact modeling of multiple-gate (MG)
MOSFETs. Long-channel core models based on the analytical potential solutions of Poisson …

Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges

F Djeffal, Z Ghoggali, Z Dibi, N Lakhdar - Microelectronics Reliability, 2009 - Elsevier
As the channel length rapidly shrinks down to the nanoscale regime, the multiple gate
MOSFETs structures have been considered as potential candidates for a CMOS device …

A charge-plasma-based transistor with induced graded channel for enhanced analog performance

C Shan, Y Wang, MT Bao - IEEE Transactions on electron …, 2016 - ieeexplore.ieee.org
In this paper, using the charge-plasma concept, we propose an effective technique to
implement a graded channel (GC) nanoscale MOSFET without the need for a separate …

A two-dimensional model for the potential distribution and threshold voltage of short-channel double-gate metal-oxide-semiconductor field-effect transistors with a …

S Dubey, PK Tiwari, S Jit - Journal of Applied Physics, 2010 - pubs.aip.org
A two-dimensional (2D) model for the threshold voltage of the short-channel double-gate
(DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) with a vertical Gaussian …

A two-dimensional analytical model for threshold voltage of short-channel triple-material double-gate metal-oxide-semiconductor field-effect transistors

PK Tiwari, S Dubey, M Singh, S Jit - Journal of Applied Physics, 2010 - pubs.aip.org
A two-dimensional (2D) analytical model for the threshold voltage of fully depleted short-
channel triple-material double-gate (DG) metal-oxide-semiconductor field-effect transistors …

Device design engineering for optimum analog/RF performance of nanoscale DG MOSFETs

RK Sharma, M Bucher - IEEE Transactions on Nanotechnology, 2012 - ieeexplore.ieee.org
Analog/RF performance of double-gate MOSFETs in the sub-20-nm regime is investigated
using ATLAS device simulator. It is shown that graded channel dual material double gate …

FinPrin: FinFET logic circuit analysis and optimization under PVT variations

Y Yang, NK Jha - IEEE Transactions on Very Large Scale …, 2013 - ieeexplore.ieee.org
Continued scaling of bulk CMOS technology is facing formidable challenges. FinFETs, with
better control of short-channel effects, offer a promising alternative for the 22-nm technology …

Analytical modelling for the current–voltage characteristics of undoped or lightly-doped symmetric double-gate MOSFETs

A Tsormpatzoglou, DH Tassis, CA Dimitriadis… - Microelectronic …, 2010 - Elsevier
An analytical drain current model for undoped (or lightly-doped) symmetric double-gate (DG)
MOSFETs is presented. This model is based on the subthreshold leakage current in weak …

Physics-based compact model for ultra-scaled FinFETs

A Yesayan, F Prégaldiny, N Chevillon, C Lallement… - Solid-State …, 2011 - Elsevier
A physical and explicit compact model for lightly doped FinFETs is presented. This design-
oriented model is valid for a large range of silicon Fin widths and lengths, using only a very …

Analytical analysis of nanoscale fully depleted Double-Gate MOSFETs including the hot-carrier degradation effects

Z Ghoggali, F Djeffal - International Journal of Electronics, 2010 - Taylor & Francis
Increased device degradation due to hot-carrier effects in nanoscale double-gate (DG)
MOSFETs is investigated. We have studied the hot-carrier degradation effects on surface …