Qulatis: A quantum error correction methodology toward lattice surgery

Y Ueno, M Kondo, M Tanaka, Y Suzuki… - … Symposium on High …, 2022 - ieeexplore.ieee.org
Due to the high error rate of a qubit, detecting and correcting errors on it is essential for fault-
tolerant quantum computing (FTQC). Surface code (SC) associated with its decoding …

Design and demonstration of an 8-bit bit-serial RSFQ microprocessor: CORE e4

Y Ando, R Sato, M Tanaka, K Takagi… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
We present a design of an 8-bit bit-serial rapid single-flux-quantum (RSFQ) microprocessor,
which is called CORE e4, and its high-speed functionality test results. The CORE e4 is …

ERSFQ 8-bit parallel arithmetic logic unit

AF Kirichenko, IV Vernik, MY Kamkar… - IEEE Transactions …, 2019 - ieeexplore.ieee.org
We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU
design employs wave-pipelined instruction execution and features modular bit-slice …

Logic design and simulation of a 128-b AES encryption accelerator based on rapid single-flux-quantum circuits

Y Zhou, GM Tang, JH Yang, PS Yu… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
A 128-b rapid single-flux-quantum (RSFQ) Advanced Encryption Standard (AES) encryption
accelerator based on bit-slice architecture is proposed for the first time. Unlike the traditional …

High-speed operation of random-access-memory-embedded microprocessor with minimal instruction set architecture based on rapid single-flux-quantum logic

R Sato, Y Hatanaka, Y Ando, M Tanaka… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
We present design and experimental results of a rapid single-flux-quantum (RSFQ) bit-serial
microprocessor with reduced-size embedded random access memories (RAMs) and with a …

Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor,

Y Yamanashi, M Tanaka, A Akimoto… - IEEE transactions on …, 2007 - ieeexplore.ieee.org
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was
designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based …

64-GHz datapath demonstration for bit-parallel SFQ microprocessors based on a gate-level-pipeline structure

R Kashima, I Nagaoka, M Tanaka… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
We successfully demonstrated an 8-bit-wide, bit-parallel datapath composed of an arithmetic
logic unit and register files for high-throughput oriented SFQ microprocessors based on a …

4-bit bit-slice arithmetic logic unit for 32-bit RSFQ microprocessors

GM Tang, K Takata, M Tanaka… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
A 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum
microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for …

SMART: A heterogeneous scratchpad memory architecture for superconductor SFQ-based systolic CNN accelerators

F Zokaee, L Jiang - MICRO-54: 54th Annual IEEE/ACM International …, 2021 - dl.acm.org
Ultra-fast & low-power superconductor single-flux-quantum (SFQ)-based CNN systolic
accelerators are built to enhance the CNN inference throughput. However, shift-register …

A majority logic synthesis framework for adiabatic quantum-flux-parametron superconducting circuits

R Cai, O Chen, A Ren, N Liu, C Ding… - Proceedings of the …, 2019 - dl.acm.org
Adiabatic Quantum-Flux-Parametron (AQFP) logic is an adiabatic superconductor logic that
has been proposed as alternative to CMOS logic with extremely high energy efficiency. In …