Two-dimensional semiconductors and transistors for future integrated circuits
L Yin, R Cheng, J Ding, J Jiang, Y Hou, X Feng… - ACS …, 2024 - ACS Publications
Silicon transistors are approaching their physical limit, calling for the emergence of a
technological revolution. As the acknowledged ultimate version of transistor channels, 2D …
technological revolution. As the acknowledged ultimate version of transistor channels, 2D …
Review of circuit level leakage minimization techniques in CMOS VLSI circuits
Ever increasing demand for portable and battery-operated systems has led to aggressive
scaling. While technology scaling facilitates faster and high-performance devices, at the …
scaling. While technology scaling facilitates faster and high-performance devices, at the …
Reliability challenges for CMOS technology qualifications with hafnium oxide/titanium nitride gate stacks
A Kerber, EA Cartier - IEEE Transactions on Device and …, 2009 - ieeexplore.ieee.org
It has been demonstrated that the introduction of HfO 2/TiN gate stacks into CMOS
technologies provides the means to continue with traditional device gate length scaling …
technologies provides the means to continue with traditional device gate length scaling …
The smallest engine transforming humanity: the past, present, and future
K Kim - 2021 IEEE International Electron Devices Meeting …, 2021 - ieeexplore.ieee.org
Semiconductors, amongst one of the most important innovations of the 20 th century, have
played a pivotal role in the creation of a digitalized, modern industrial society. The global …
played a pivotal role in the creation of a digitalized, modern industrial society. The global …
Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- Stacks
A Kerber, SA Krishnan… - IEEE Electron Device …, 2009 - ieeexplore.ieee.org
A novel voltage-ramp-stress (VRS) methodology is introduced for bias temperature
instability testing of metal-gate/high-k (MG/HK) CMOS devices. Results from VRS are …
instability testing of metal-gate/high-k (MG/HK) CMOS devices. Results from VRS are …
Compact design of low power standard ternary inverter based on OFF-state current mechanism using nano-CMOS technology
We propose a novel standard ternary inverter (STI) based on nanoscale CMOS technology
for a compact design of multivalued logic. Using the gate bias independent OFF-state …
for a compact design of multivalued logic. Using the gate bias independent OFF-state …
A discussion on SRAM circuit design trend in deeper nanometer-scale technologies
H Yamauchi - IEEE Transactions on Very Large Scale …, 2009 - ieeexplore.ieee.org
This paper compares area scaling capabilities of many kinds of SRAM margin-assist
solutions for VT variability issues, which are based on various efforts by not only the cell …
solutions for VT variability issues, which are based on various efforts by not only the cell …
High-κ/Metal Gate Science and Technology
High-κ/metal gate technology is on the verge of replacing conventional oxynitride dielectrics
in state-of-the-art transistors for both high-performance and low-power applications. In this …
in state-of-the-art transistors for both high-performance and low-power applications. In this …
A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length
At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in
overcoming the increased leakage current (Ioff). The invention of high-k/metal gate …
overcoming the increased leakage current (Ioff). The invention of high-k/metal gate …
Parasitic capacitances: Analytical models and impact on circuit-level performance
Parasitic capacitances have become a main issue for advanced technology nodes. In this
paper, we develop analytical models for parasitic capacitance components for several …
paper, we develop analytical models for parasitic capacitance components for several …