A review on radiation‐hardened memory cells for space and terrestrial applications
Over the past four decades, single event upset (SEU) and single event multiple node upset
(SEMNU) have become the major issues in the memory area. Moreover, these upsets are …
(SEMNU) have become the major issues in the memory area. Moreover, these upsets are …
Quadruple and sextuple cross-coupled SRAM cell designs with optimized overhead for reliable applications
Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable
to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This …
to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This …
Quadruple cross-coupled latch-based 10T and 12T SRAM bit-cell designs for highly reliable terrestrial applications
J Jiang, Y Xu, W Zhu, J **ao… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in
130 nm CMOS technology. The QUCCE 10T and 12T are about 2× and 3.4× the minimum …
130 nm CMOS technology. The QUCCE 10T and 12T are about 2× and 3.4× the minimum …
Novel speed-and-power-optimized SRAM cell designs with enhanced self-recoverability from single-and double-node upsets
The continuous advancement of CMOS technologies makes SRAMs more and more
sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell …
sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell …
A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets
C Qi, L **ao, T Wang, J Li, L Li - IEEE Transactions on Device …, 2016 - ieeexplore.ieee.org
In this paper, a highly reliable radiation hardened by design memory cell (RHD12) using 12
transistors in a 65-nm CMOS commercial technology is proposed. Combining with layout …
transistors in a 65-nm CMOS commercial technology is proposed. Combining with layout …
Design of soft-error-aware SRAM with multi-node upset recovery for aerospace applications
To achieve improved speed of operation, a higher integration density and lower power
dissipation, transistors are being scaled aggressively. This trend has reduced the critical …
dissipation, transistors are being scaled aggressively. This trend has reduced the critical …
Soft-error resilient read decoupled SRAM with multi-node upset recovery for space applications
Space consists of high-energy particles and high-temperature fluctuations, which causes
single event upsets (SEUs). Conventional 6T static random access memory (SRAM) is …
single event upsets (SEUs). Conventional 6T static random access memory (SRAM) is …
Highly stable low power radiation hardened memory-by-design SRAM for space applications
In space, due to high energy particles, which cause single event upsets (SEUs), the
traditional 6T SRAM cell becomes more susceptible to soft-error. In order to address this, a …
traditional 6T SRAM cell becomes more susceptible to soft-error. In order to address this, a …
Novel low-power and highly reliable radiation hardened memory cell for 65 nm CMOS technology
J Guo, L **ao, Z Mao - … Transactions on Circuits and Systems I …, 2014 - ieeexplore.ieee.org
In this paper, a novel low-power and highly reliable radiation hardened memory cell (RHM-
12T) using 12 transistors is proposed to provide enough immunity against single event upset …
12T) using 12 transistors is proposed to provide enough immunity against single event upset …
Design of area-efficient and highly reliable RHBD 10T memory cell for aerospace applications
J Guo, L Zhu, Y Sun, H Cao, H Huang… - … Transactions on Very …, 2018 - ieeexplore.ieee.org
In this brief, based on upset physical mechanism together with reasonable transistor size, a
robust 10T memory cell is first proposed to enhance the reliability level in aerospace …
robust 10T memory cell is first proposed to enhance the reliability level in aerospace …