InP-based transistor fabrication
5,061,644 5,079,616 5,091,333 5,091,767 5,093,699 5,098,850 5,105,247 5,108,947
5,156,995 5,159,413 5,164.359 5,166,767 5,223,043 5,236,546 5,238,869 5,256,594 …
5,156,995 5,159,413 5,164.359 5,166,767 5,223,043 5,236,546 5,238,869 5,256,594 …
Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
(65) Prior Publication Data(Continued) US 2011 FOO49568 A1 Mar. 3, 2011 OTHER
PUBLICATIONS Related US Application Data 68 Applied Physics Letters 7, pp. 774-779 …
PUBLICATIONS Related US Application Data 68 Applied Physics Letters 7, pp. 774-779 …
Hybrid fin field-effect transistor structures and related methods
MT Currie - US Patent 8,183,627, 2012 - Google Patents
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5.426, 316 5.439, 843 5,442,205 5,461,243 5,461,250 5,462,883 5,476,813 5,479,033 …
5.426, 316 5.439, 843 5,442,205 5,461,243 5,461,250 5,462,883 5,476,813 5,479,033 …
Tri-gate field-effect transistors formed by aspect ratio trap**
AJ Lochtefeld - US Patent 7,799,592, 2010 - Google Patents
Semiconductor structures include a trench formed proximate a substrate including a first
semiconductor material. A crystalline material including a second semiconductor material …
semiconductor material. A crystalline material including a second semiconductor material …
Defect reduction using aspect ratio trap**
J Bai, JS Park, AJ Lochtefeld - US Patent 8,173,551, 2012 - Google Patents
US8173551B2 - Defect reduction using aspect ratio trap** - Google Patents
US8173551B2 - Defect reduction using aspect ratio trap** - Google Patents Defect …
US8173551B2 - Defect reduction using aspect ratio trap** - Google Patents Defect …
Strained finFETs and method of manufacture
A semiconductor structure and method of manufacturing is provided. The method of
manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a …
manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a …
Semiconductor sensor structures with reduced dislocation defect densities
Z Cheng, JG Fiorenza, C Sheen… - US Patent 8,253,211, 2012 - Google Patents
5,091,333 5,091,767 5,093,699 5,098,850 5,105,247 5,108,947 5,156,995 5,159,413
5,164.359 5,166,767 5,223,043 5,236,546 5,238,869 5,256,594 5,269,852 5,269,876 …
5,164.359 5,166,767 5,223,043 5,236,546 5,238,869 5,256,594 5,269,852 5,269,876 …
Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
J Li, AJ Lochtefeld - US Patent 9,153,645, 2015 - Google Patents
US9153645B2 - Lattice-mismatched semiconductor structures with reduced dislocation
defect densities and related methods for device fabrication - Google Patents US9153645B2 …
defect densities and related methods for device fabrication - Google Patents US9153645B2 …
Lattice-mismatched semiconductor structures and related methods for device fabrication
AJ Lochtefeld - US Patent 7,777,250, 2010 - Google Patents
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et al. 5,091,767 A 2f1992 Bean et al. 5,093,699 A 3, 1992 Weichold et al. 5,105,247 A …
Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited
area regions having upper por tions Substantially exhausted of threading dislocations, as …
area regions having upper por tions Substantially exhausted of threading dislocations, as …