Brief overview of the impact of thermal stress on the reliability of through silicon via: Analysis, characterization, and enhancement

S Tang, J Chen, YB Hu, C Yu, H Lu, S Zhang… - Materials Science in …, 2024 - Elsevier
Abstract Three-dimensional (3D) integration is considered an effective approach to extend
and expand Moore's Law. Among them, Through-Silicon Via (TSV) technology provides …

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

M Jung, J Mitra, DZ Pan, SK Lim - Proceedings of the 48th Design …, 2011 - dl.acm.org
In this work, we propose an efficient and accurate full-chip thermo-mechanical stress and
reliability analysis tool and design optimization methodology to alleviate mechanical …

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study

K Athikulwongse, A Chakraborty… - 2010 IEEE/ACM …, 2010 - ieeexplore.ieee.org
Through-silicon via (TSV) fabrication causes tensile stress around TSVs which results in
significant carrier mobility variation in the devices in their neighborhood. Keep-out zone …

Effect of thermal stresses on carrier mobility and keep-out zone around through-silicon vias for 3-D integration

SK Ryu, KH Lu, T Jiang, JH Im… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
Three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an
effective solution to overcome the wiring limit imposed on device density and performance …

Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs

X Zhao, J Minz, SK Lim - IEEE Transactions on Components …, 2010 - ieeexplore.ieee.org
This paper focuses on low-power and low-slew clock network design and analysis for
through-silicon via (TSV) based three-dimensional stacked ICs (3D ICs). First, we investigate …

TSV-based 3-D ICs: Design methods and tools

T Lu, C Serafy, Z Yang, SK Samal… - … on Computer-Aided …, 2017 - ieeexplore.ieee.org
Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …

Overcoming variations in nanometer-scale technologies

SS Sapatnekar - IEEE Journal on Emerging and Selected …, 2011 - ieeexplore.ieee.org
Nanometer-scale circuits are fundamentally different from those built in their predecessor
technologies in that they are subject to a wide range of new effects that induce on-chip …

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

M Jung, J Mitra, DZ Pan, SK Lim - Communications of the ACM, 2014 - dl.acm.org
Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to
offer new levels of efficiency, power, performance, and form-factor advantages over the …

TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test

K Chakrabarty, S Deutsch… - 2012 IEEE International …, 2012 - ieeexplore.ieee.org
3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) have emerged as a
promising solution for overcoming interconnect and power bottlenecks in IC design …

Thermal and mechanical reliability of thermal through-silicon vias in three-dimensional integrated circuits

C Qu, R Dai, J Zheng, Y Hu, J Zhang - Microelectronics Reliability, 2023 - Elsevier
This research aims to explore the influences of shapes, structures, and arrangements of
thermal through-silicon vias (TTSVs) on the thermal and mechanical reliability of a three …