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ECC-united cache: Maximizing efficiency of error detection/correction codes in associative cache memories
Error Detection/Correction Codes (EDCs/ECCs) are the most conventional approaches to
protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is …
protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is …
[Retracted] Virtual Digital Communication Feature Fusion Based on Virtual Augmented Reality
X Zhang - Security and Communication Networks, 2022 - Wiley Online Library
In order to have a deeper understanding of the integration of virtual digital communication
characteristics, it is studied and combined with virtual augmented reality technology. The …
characteristics, it is studied and combined with virtual augmented reality technology. The …
Voting Margin: A Scheme for Error-Tolerant k Nearest Neighbors Classifiers for Machine Learning
Machine learning (ML) techniques such as classifiers are used in many applications, some
of which are related to safety or critical systems. In this case, correct processing is a strict …
of which are related to safety or critical systems. In this case, correct processing is a strict …
ReBEC: A replacement-based energy-efficient fault-tolerance design for associative caches
X Gao, N Cui, J Nian, Z Liang, J Gao, H Liu… - Future Generation …, 2024 - Elsevier
Severe environments like space radiation can induce soft errors in processors and incur
unexpected bit-flips. Error Detection and Correction (EDAC) is a crucial method to protect …
unexpected bit-flips. Error Detection and Correction (EDAC) is a crucial method to protect …
Two-Dimensional Protection Code for Virtual Page Information in Translation Lookaside Buffers
X Gao, N Cui, J Nian, H Liu, M Yang - Electronics, 2024 - mdpi.com
Severe conditions such as high-energy particle strikes may induce soft errors in on-chip
memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual …
memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual …
[PDF][PDF] Soft Error Rate Measurements through ACE Analysis in TLB Structures of CPUs
KMI Sgouras - 2024 - pergamos.lib.uoa.gr
In recent years, there has been a decrease in the minimum feature size of the transistors in
integrated circuits. As a result, the vulnerability of CPU components has increased. An …
integrated circuits. As a result, the vulnerability of CPU components has increased. An …
Reducing false positives due to double adjacent errors in instruction TLBs
Translation lookaside buffers (TLBs) are cache structures used to make the translation
process between virtual pages and physical pages faster. Instruction TLBs store the virtual …
process between virtual pages and physical pages faster. Instruction TLBs store the virtual …
[PDF][PDF] Microarchitecture-level reliability assessment of multi-bit upsets in processors
CM Gavanas - 2019 - core.ac.uk
The continuing decrease in feature sizes for modern Integrated Circuits (ICs) leads to an
ever-important role of reliability and vulnerability assessments on the core in early stages of …
ever-important role of reliability and vulnerability assessments on the core in early stages of …