Designs of two quadruple-node-upset self-recoverable latches for highly robust computing in harsh radiation environments
This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-
recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low …
recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low …
Information assurance through redundant design: A novel TNU error-resilient latch for harsh radiation environment
In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly
sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context …
sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context …
Novel quadruple-node-upset-tolerant latch designs with optimized overhead for reliable computing in harsh radiation environments
With the rapid advancement of CMOS technologies, nano-scale CMOS latches have
become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations …
become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations …
Novel low cost, double-and-triple-node-upset-tolerant latch designs for nano-scale CMOS
A Yan, C Lai, Y Zhang, J Cui, Z Huang… - … on Emerging Topics …, 2018 - ieeexplore.ieee.org
This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs.
First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch …
First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch …
LDAVPM: A latch design and algorithm-based verification protected against multiple-node-upsets in harsh radiation environments
In deep nano-scale and high-integration CMOS technologies, storage circuits have become
increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include …
increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include …
Two double-node-upset-hardened flip-flop designs for high-performance applications
The continuous advancement of complementary metal-oxide-semiconductor technologies
makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as …
makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as …
Double-node-upset-resilient latch design for nanoscale CMOS technology
A Yan, Z Huang, M Yi, X Xu, Y Ouyang… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS
technology. The latch comprises three interlocked single-node-upset-resilient cells and each …
technology. The latch comprises three interlocked single-node-upset-resilient cells and each …
A highly robust and low-power real-time double node upset self-healing latch for radiation-prone applications
This work presents a single event double node upset (SEDNU) self-healing (DNUSH) latch
to meet the high-robustness requirement of the applications used in a harsh radiation …
to meet the high-robustness requirement of the applications used in a harsh radiation …
Quadruple cross-coupled dual-interlocked-storage-cells-based multiple-node-upset-tolerant latch designs
First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch,
featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element …
featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element …
Low-overhead triple-node-upset-tolerant latch design in 28-nm CMOS
X Chen, Y Bai, J Cao, L Wang, X Zhou… - … Transactions on Very …, 2023 - ieeexplore.ieee.org
As the feature size of the nanoscale CMOS keeps scaling down, the charge sharing effect is
becoming more and more prominent, and the occurrence possibility of the triple-node upset …
becoming more and more prominent, and the occurrence possibility of the triple-node upset …