A survey of processors with explicit multithreading

T Ungerer, B Robič, J Šilc - ACM Computing Surveys (CSUR), 2003 - dl.acm.org
Hardware multithreading is becoming a generally applied technique in the next generation
of microprocessors. Several multithreaded processors are announced by industry or already …

[KSIĄŻKA][B] Computer architecture: a quantitative approach

JL Hennessy, DA Patterson - 2011 - books.google.com
Computer Architecture: A Quantitative Approach, Fifth Edition, explores the ways that
software and technology in the cloud are accessed by digital media, such as cell phones …

[KSIĄŻKA][B] Parallel computer architecture: a hardware/software approach

D Culler, JP Singh, A Gupta - 1999 - books.google.com
The most exciting development in parallel computer architecture is the convergence of
traditionally disparate approaches on a common machine structure. This book explains the …

Symbiotic jobscheduling for a simultaneous multithreaded processor

A Snavely, DM Tullsen - … of the ninth international conference on …, 2000 - dl.acm.org
Simultaneous Multithreading machines fetch and execute instructions from multiple
instruction streams to increase system utilization and speedup the execution of jobs. When …

Multithreaded processors

T Ungerer, B Robič, J Šilc - The Computer Journal, 2002 - academic.oup.com
The instruction-level parallelism found in a conventional instruction stream is limited. Studies
have shown the limits of processor utilization even for today's superscalar microprocessors …

Simultaneous multithreading: A platform for next-generation processors

SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm… - IEEE micro, 1997 - ieeexplore.ieee.org
Simultaneous multithreading is a processor design which consumes both thread-level and
instruction-level parallelism. In SMT processors, thread-level parallelism can come from …

[PDF][PDF] Dynamic partitioning of shared cache memory

GE Suh, L Rudolph, S Devadas - The Journal of …, 2004 - people.csail.mit.edu
This paper proposes dynamic cache partitioning amongst simultaneously executing
processes/threads. We present a general partitioning scheme that can be applied to set …

[KSIĄŻKA][B] Multiprocessor systems-on-chips

A Jerraya, W Wolf - 2004 - books.google.com
Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …

A framework for performance modeling and prediction

A Snavely, L Carrington, N Wolter… - SC'02: Proceedings …, 2002 - ieeexplore.ieee.org
Cycle-accurate simulation is far too slow for modeling the expected performance of full
parallel applications on large HPC systems. And just running an application on a system …

A new memory monitoring scheme for memory-aware scheduling and partitioning

GE Suh, S Devadas, L Rudolph - … International Symposium on …, 2002 - ieeexplore.ieee.org
We propose a low overhead, online memory monitoring scheme utilizing a set of novel
hardware counters. The counters indicate the marginal gain in cache hits as the size of the …