A survey of processors with explicit multithreading
T Ungerer, B Robič, J Šilc - ACM Computing Surveys (CSUR), 2003 - dl.acm.org
Hardware multithreading is becoming a generally applied technique in the next generation
of microprocessors. Several multithreaded processors are announced by industry or already …
of microprocessors. Several multithreaded processors are announced by industry or already …
[KSIĄŻKA][B] Computer architecture: a quantitative approach
JL Hennessy, DA Patterson - 2011 - books.google.com
Computer Architecture: A Quantitative Approach, Fifth Edition, explores the ways that
software and technology in the cloud are accessed by digital media, such as cell phones …
software and technology in the cloud are accessed by digital media, such as cell phones …
[KSIĄŻKA][B] Parallel computer architecture: a hardware/software approach
The most exciting development in parallel computer architecture is the convergence of
traditionally disparate approaches on a common machine structure. This book explains the …
traditionally disparate approaches on a common machine structure. This book explains the …
Symbiotic jobscheduling for a simultaneous multithreaded processor
Simultaneous Multithreading machines fetch and execute instructions from multiple
instruction streams to increase system utilization and speedup the execution of jobs. When …
instruction streams to increase system utilization and speedup the execution of jobs. When …
Multithreaded processors
T Ungerer, B Robič, J Šilc - The Computer Journal, 2002 - academic.oup.com
The instruction-level parallelism found in a conventional instruction stream is limited. Studies
have shown the limits of processor utilization even for today's superscalar microprocessors …
have shown the limits of processor utilization even for today's superscalar microprocessors …
Simultaneous multithreading: A platform for next-generation processors
Simultaneous multithreading is a processor design which consumes both thread-level and
instruction-level parallelism. In SMT processors, thread-level parallelism can come from …
instruction-level parallelism. In SMT processors, thread-level parallelism can come from …
[PDF][PDF] Dynamic partitioning of shared cache memory
This paper proposes dynamic cache partitioning amongst simultaneously executing
processes/threads. We present a general partitioning scheme that can be applied to set …
processes/threads. We present a general partitioning scheme that can be applied to set …
[KSIĄŻKA][B] Multiprocessor systems-on-chips
Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …
A framework for performance modeling and prediction
Cycle-accurate simulation is far too slow for modeling the expected performance of full
parallel applications on large HPC systems. And just running an application on a system …
parallel applications on large HPC systems. And just running an application on a system …
A new memory monitoring scheme for memory-aware scheduling and partitioning
We propose a low overhead, online memory monitoring scheme utilizing a set of novel
hardware counters. The counters indicate the marginal gain in cache hits as the size of the …
hardware counters. The counters indicate the marginal gain in cache hits as the size of the …