Machine learning for electronic design automation: A survey

G Huang, J Hu, Y He, J Liu, M Ma, Z Shen… - ACM Transactions on …, 2021 - dl.acm.org
With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

MLCAD: A survey of research in machine learning for CAD keynote paper

M Rapp, H Amrouch, Y Lin, B Yu… - … on Computer-Aided …, 2021 - ieeexplore.ieee.org
Due to the increasing size of integrated circuits (ICs), their design and optimization phases
(ie, computer-aided design, CAD) grow increasingly complex. At design time, a large design …

Enhanced Lithographic Hotspot Detection via Multi-Task Deep Learning with Synthetic Pattern Generation

S Chen, Z Shao, Y Niu, L Fan - IEEE Open Journal of the …, 2024 - ieeexplore.ieee.org
Lithographic hotspot detection is crucial for ensuring manufacturability and yield in
advanced integrated circuit (IC) designs. While machine learning approaches have shown …

High-definition routing congestion prediction for large-scale FPGAs

MB Alawieh, W Li, Y Lin, L Singhal… - 2020 25th Asia and …, 2020 - ieeexplore.ieee.org
To speed up the FPGA placement and routing closure, we propose a novel approach to
predict the routing congestion map for large-scale FPGA designs at the placement stage …

GeniusRoute: A new analog routing paradigm using generative neural network guidance

K Zhu, M Liu, Y Lin, B Xu, S Li, X Tang… - 2019 IEEE/ACM …, 2019 - ieeexplore.ieee.org
Due to sensitive layout-dependent effects and varied performance metrics, analog routing
automation for performance-driven layout synthesis is difficult to generalize. Existing …

DAMO: Deep agile mask optimization for full chip scale

G Chen, W Chen, Y Ma, H Yang, B Yu - Proceedings of the 39th …, 2020 - dl.acm.org
Continuous scaling of the VLSI system leaves a great challenge on manufacturing, thus
optical proximity correction (OPC) is widely applied in conventional design flow for …

Lithobench: Benchmarking ai computational lithography for semiconductor manufacturing

S Zheng, H Yang, B Zhu, B Yu… - Advances in Neural …, 2024 - proceedings.neurips.cc
Computational lithography provides algorithmic and mathematical support for resolution
enhancement in optical lithography, which is the critical step in semiconductor …

DevelSet: Deep neural level set for instant mask optimization

G Chen, Z Yu, H Liu, Y Ma, B Yu - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
As one of the key techniques for resolution enhancement technologies (RETs), optical
proximity correction (OPC) suffers from prohibitive computational costs as feature sizes …

Generic lithography modeling with dual-band optics-inspired neural networks

H Yang, Z Li, K Sastry, S Mukhopadhyay… - Proceedings of the 59th …, 2022 - dl.acm.org
Lithography simulation is a critical step in VLSI design and optimization for
manufacturability. Existing solutions for highly accurate lithography simulation with rigorous …

Powernet: SOI lateral power device breakdown prediction with deep neural networks

J Chen, MB Alawieh, Y Lin, M Zhang, J Zhang… - IEEE …, 2020 - ieeexplore.ieee.org
The breakdown performance is a critical metric for power device design. This paper explores
the feasibility of efficiently predicting the breakdown performance of silicon on insulator (SOI) …