Double-Gate Tunnel FET With High- Gate Dielectric

K Boucart, AM Ionescu - IEEE transactions on electron devices, 2007 - ieeexplore.ieee.org
In this paper, we propose and validate a novel design for a double-gate tunnel field-effect
transistor (DG tunnel FET), for which the simulations show significant improvements …

HfAlO3 films for gate dielectrics

KY Ahn, L Forbes - US Patent 7,554,161, 2009 - Google Patents
5,032,545 5,049,516 5,055,319 5,080,928 5,089,084 5, 198,029 5,302.461 5,595,606
5,614,026 5,621,681 5,625,233 5,674.563 5,674,574 5,698,022 5,735,960 5,744,374 …

Methods, systems, and apparatus for uniform chemical-vapor depositions

KY Ahn - US Patent 6,852,167, 2005 - Google Patents
4920, 071 4920, 396 4.948, 937 4,962,879 4987, 089 4,993,358 5.001526 5,006,192
5,017,504 5,021,355 5,028,977 5,032,545 5,080,928 5,089,084 5,097,291 5,102,817 …

Review on high-k dielectrics reliability issues

G Ribes, J Mitard, M Denais, S Bruyere… - … on Device and …, 2005 - ieeexplore.ieee.org
High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in
CMOS advanced technologies. One of the important challenges in integrating these …

Effect of gate engineering in double-gate MOSFETs for analog/RF applications

A Sarkar, AK Das, S De, CK Sarkar - Microelectronics Journal, 2012 - Elsevier
This work uncovers the potential benefit of fully-depleted short-channel triple-material
double-gate (TM-DG) SOI MOSFET in the context of RF and analog performance …

An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design

P Ghosh, S Haldar, RS Gupta… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
In this paper, an extensive study on the intermodulation distortion and the linearity of gate-
material-engineered cylindrical-gate MOSFET (GME CGT MOSFET) has been done, and the …

[KIRJA][B] Low-power electronics design

C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …

[KIRJA][B] Managing temperature effects in nanoscale adaptive systems

D Wolpert, P Ampadu - 2011 - books.google.com
This book discusses new techniques for detecting, controlling, and exploiting the impacts of
temperature variations on nanoscale circuits and systems. A new sensor system is …

Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

M Cassé, L Thevenod, B Guillaumot… - … on Electron Devices, 2006 - ieeexplore.ieee.org
Electron and hole mobility in HfO/sub 2//metal gate MOSFETs is deeply studied through low-
temperature measurements down to 4.2 K. Original technological splits allow the …

Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed

KY Ahn, L Forbes - US Patent 7,199,023, 2007 - Google Patents
Fuyuki, Takashi, et al.,“Initial stage of ultra-thin SiO2 formation at low temperatures using
activated oxygen'. Applied Surface Science,(1997), pp. 123-126. Gartner, M." …