FPGA dynamic and partial reconfiguration: A survey of architectures, methods, and applications
Dynamic and partial reconfiguration are key differentiating capabilities of field
programmable gate arrays (FPGAs). While they have been studied extensively in academic …
programmable gate arrays (FPGAs). While they have been studied extensively in academic …
A review on SEU mitigation techniques for FPGA configuration memory
Single event upset (SEU) has become one of the major threats to dependable application
development targeted at safety systems in field programmable gate arrays (FPGAs). This …
development targeted at safety systems in field programmable gate arrays (FPGAs). This …
A novel design methodology for implementing reliability-aware systems on SRAM-based FPGAs
This paper presents a novel design flow for the implementation of digital systems onto
SRAM-based FPGAs with soft error mitigation properties. Traditional fault …
SRAM-based FPGAs with soft error mitigation properties. Traditional fault …
[PDF][PDF] A self-adaptive resilient method for implementing and managing the high-reliability processing system
J Chen - 2023 - researchgate.net
As a result of CMOS scaling, radiation-induced Single-Event Effects (SEEs) in electronic
circuits became a critical reliability issue for modern Integrated Circuits (ICs) operating under …
circuits became a critical reliability issue for modern Integrated Circuits (ICs) operating under …
Improving the robustness of a softcore processor against SEUs by using TMR and partial reconfiguration
Y Ichinomiya, S Tanoue, M Amagasaki… - 2010 18th IEEE …, 2010 - ieeexplore.ieee.org
SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event
upset (SEU), which is induced by radiation effect. This paper presents a technique for …
upset (SEU), which is induced by radiation effect. This paper presents a technique for …
Approximated user-perspective rendering in tablet-based augmented reality
M Tomioka, S Ikeda, K Sato - 2013 IEEE International …, 2013 - ieeexplore.ieee.org
This study addresses the problem of geometric consistency between displayed images and
real scenes in augmented reality using a video see-through hand-held display or tablet. To …
real scenes in augmented reality using a video see-through hand-held display or tablet. To …
SEU simulation framework for **linx FPGA: First step towards testing fault tolerant systems
In the paper, the SEU simulation framework for testing fault tolerant system designs
implemented into FPGA is presented. The framework is based on SEU generation outside …
implemented into FPGA is presented. The framework is based on SEU generation outside …
FTT-NAS: Discovering fault-tolerant convolutional neural architecture
With the fast evolvement of embedded deep-learning computing systems, applications
powered by deep learning are moving from the cloud to the edge. When deploying neural …
powered by deep learning are moving from the cloud to the edge. When deploying neural …
Automated design and usage of the Fault-Tolerant dynamic partial reconfiguration controller for FPGAs
This article presents a new design automation method for Fault-Tolerant (FT) systems
implemented on dynamically reconfigurable Field Programmable Gate Arrays (FPGAs). The …
implemented on dynamically reconfigurable Field Programmable Gate Arrays (FPGAs). The …
Fault tolerant system design and SEU injection based testing
The methodology for the design and testing of fault tolerant systems implemented into an
FPGA platform with different types of diagnostic techniques is presented in this paper. Basic …
FPGA platform with different types of diagnostic techniques is presented in this paper. Basic …