In distributed memory multicomputers, local memory accesses are much faster than those
involving interprocessor communication. For the sake of reducing or even eliminating the …

Logic diagnosis is the process of isolating possible sources of observed errors in a defective
circuit, so that physical failure analysis can be performed to determine the root cause of such …

This paper presents a comprehensive framework for logic diagnosis consisting of two main
phases. In the first phase, a set of suspected faulty sites is obtained by applying an approach …

Multiple voltage is an effective dynamic power reduction design technique commonly used
in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing …

In this paper, we present a diagnosis methodology targeting the whole set of bridging faults
leading to either static or dynamic faulty behavior. The adopted diagnosis algorithm resorts …

Innovative manufacturing processes allow the integration of billions of transistors into a
single chip, and the implementation of extremely dense designs, but they also come with …

This paper addresses the problem of logic diagnosis of System-on-Chip (SoC). We propose
a diagnosis approach based on a matching algorithm between a set of predicted failures …

This paper presents an industrial case study on logic diagnosis targeting system-on-chip
(SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we …

The concept of fault model free diagnosis is combined with cause-effect analysis in digital
systems represented as networks of functional blocks. We consider the diagnosis as a task …

The amount of die area consumed by scan chains and scan control circuit can range from
15%~ 30%, and scan chain failures account for almost 50% of chip failures. As the …