Conventional in-memory computing (IMC) architectures consist of analog memristive
crossbars to accelerate matrix-vector multiplication (MVM), and digital functional units to …

Multiported high-performance on-die memories occupy significantly more die area than a
comparable single-port memory. Among various multiport memory topologies, the 1-read …

A High-Speed High-Density 1R1W two port 32Kbit () SRAM with single port 6T bitcell macro
is proposed. A read-then-write (RTW) double pump CLK generation circuit with tracking …

A 128-kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in
28-nm FD-SOI technology is presented. An ideal power management scenario in a single …

In this article, we present an energy-efficient high bandwidth array design using 0.0300-high-
performance SRAM bitcell on Intel 4 CMOS technology. By employing a unique combination …

An effective design is proposed to reduce dynamic power consumption for a common clock
synchronous two-read/write (2RW) dual-port (DP) 8T static random access memory (SRAM) …

In this paper, we characterize the interplay between power consumption and performance of
a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd …

In this paper, we present an ultra-low voltage oneport static random access memory (SRAM)
compiler targeting small to medium array sizes to provide a smaller area solution compared …

System-on-Chip (SoC) designs contain a variety of IP blocks which use multiport memories
to improve performance by enabling multiple simultaneous operations in the same memory …

This paper presents a novel resonating inductor-based supply boosting scheme for low-
voltage static random-access memories and logic in deep 14-nm silicon on insulator (SOI) …