Strain: A solution for higher carrier mobility in nanoscale MOSFETs
M Chu, Y Sun, U Aghoram… - Annual Review of …, 2009 - annualreviews.org
Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive
performance improvements over the past 10 years by incorporating strained silicon (Si) …
performance improvements over the past 10 years by incorporating strained silicon (Si) …
Germanium channel MOSFETs: Opportunities and challenges
This paper reviews progress and current critical issues with respect to the integration of
germanium (Ge) surface-channel MOSFET devices as well as strained-Ge buried-channel …
germanium (Ge) surface-channel MOSFET devices as well as strained-Ge buried-channel …
[書籍][B] Handbook of semiconductor manufacturing technology
Y Nishi, R Doering - 2000 - books.google.com
The Handbook of Semiconductor Manufacturing Technology describes the individual
processes and manufacturing control, support, and infrastructure technologies of silicon …
processes and manufacturing control, support, and infrastructure technologies of silicon …
Growth and transport properties of complementary germanium nanowire field-effect transistors
AB Greytak, LJ Lauhon, MS Gudiksen… - Applied Physics …, 2004 - pubs.aip.org
n-and p-type Ge nanowires were synthesized by a multistep process in which axial
elongation, via vapor–liquid–solid (VLS) growth, and do** were accomplished in separate …
elongation, via vapor–liquid–solid (VLS) growth, and do** were accomplished in separate …
Integration of germanium-on-insulator and silicon MOSFETs on a silicon substrate
J Feng, Y Liu, PB Griffin… - IEEE Electron Device …, 2006 - ieeexplore.ieee.org
The monolithic integration of germanium-on-insulator (GeOI) p-MOSFETs with silicon n-
MOSFETs on a silicon substrate is demonstrated. The GeOI p-MOSFETs are fabricated on …
MOSFETs on a silicon substrate is demonstrated. The GeOI p-MOSFETs are fabricated on …
Low-temperature fabrication and characterization of Ge-on-insulator structures
Ge-on-insulator structures have been fabricated by wafer bonding and layer transfer
techniques. Ultralow bonding temperatures of 150–300 C are employed in order to suppress …
techniques. Ultralow bonding temperatures of 150–300 C are employed in order to suppress …
Top-gated graphene field-effect-transistors formed by decomposition of SiC
Top-gated, few-layer graphene field-effect transistors (FETs) fabricated on thermally
decomposed semi-insulating 4 H-Si C substrates are demonstrated. Physical vapor …
decomposed semi-insulating 4 H-Si C substrates are demonstrated. Physical vapor …
High-quality single-crystal Ge on insulator by liquid-phase epitaxy on Si substrates
Y Liu, MD Deal, JD Plummer - Applied Physics Letters, 2004 - pubs.aip.org
Ge on insulator GOI is desired to obtain metal-oxide-semiconductor transistors with high
performance and low leakage current. We have developed a method to make GOI based on …
performance and low leakage current. We have developed a method to make GOI based on …
Defect levels of dangling bonds in silicon and germanium through hybrid functionals
Defect levels of dangling bonds in silicon and germanium are determined within their
respective band gaps through the use of hybrid density functionals. To validate our …
respective band gaps through the use of hybrid density functionals. To validate our …
Generalized effective-mass approach for n-type metal-oxide-semiconductor field-effect transistors on arbitrarily oriented wafers
The general theory for quantum simulation of cubic semiconductor n-type metal-oxide-
semiconductor field-effect transistors is presented within the effective-mass equation …
semiconductor field-effect transistors is presented within the effective-mass equation …