High-throughput VLSI architectures for VLSI signal processing

High-Speed Vedic Multiplier Implementation Using Memristive and Speculative Adders

B Ande, LD Kalidindi, PK Mallula… - 2022 International …, 2022 - ieeexplore.ieee.org
In ALU's, among accumulators and various other signal processing modules, the most
significant operating block is multipliers. Due to the requirement of minimum delay, special …
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Design of a Pipeline Computing Module as Part of a Specialized VLSI

I Tarasov, D Lyulyava, N Duksin, I Duksina - International Conference on …, 2023 - Springer
The article discusses the process of designing a computing node based on a synchronous
pipelined architecture for operation as part of a specialized VLSI. During the design process …
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