Considerations for ultimate CMOS scaling
KJ Kuhn - IEEE transactions on Electron Devices, 2012 - ieeexplore.ieee.org
This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
The challenges of advanced CMOS process from 2D to 3D
HH Radamson, Y Zhang, X He, H Cui, J Li, J **: successes and challenges for the next generation Ge devices
F Sgarbossa - Materials Science in Semiconductor Processing, 2023 - Elsevier
The growing interest in nanoelectronics and photonics, combined with the development of
new germanium-based devices, provide the impetus to develop new do** methods …
new germanium-based devices, provide the impetus to develop new do** methods …
Controlling BTBT-induced parasitic BJT action in junctionless FETs using a hybrid channel
In this brief, we demonstrate for the first time that the presence of a hybrid channel, which
consists of ap+ layer below the n+ active device layer in a junctionless (JL) FET, leads to a …
consists of ap+ layer below the n+ active device layer in a junctionless (JL) FET, leads to a …
Monolayer do** of silicon through grafting a tailored molecular phosphorus precursor onto oxide-passivated silicon surfaces
T Alphazan, L Mathey, M Schwarzwalder… - Chemistry of …, 2016 - ACS Publications
Monolayer do** (MLD) of silicon substrates at the nanoscale is a powerful method to
provide controlled doses of dopants and defect-free materials. However, this approach …
provide controlled doses of dopants and defect-free materials. However, this approach …
[BOOK][B] FinFET devices for VLSI circuits and systems
SK Saha - 2020 - taylorfrancis.com
To surmount the continuous scaling challenges of MOSFET devices, FinFETs have emerged
as the real alternative for use as the next generation device for IC fabrication technology …
as the real alternative for use as the next generation device for IC fabrication technology …
FinFET with encased air-gap spacers for high-performance and low-energy circuits
AB Sachid, YM Huang, YJ Chen… - IEEE Electron …, 2016 - ieeexplore.ieee.org
We experimentally demonstrate n-channel bulk FinFET with encased air-gap spacers.
Encased air gap in the spacer region is formed by depositing carbon sidewalls, encasing …
Encased air gap in the spacer region is formed by depositing carbon sidewalls, encasing …