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Considerations for ultimate CMOS scaling
KJ Kuhn - IEEE transactions on Electron Devices, 2012 - ieeexplore.ieee.org
This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
The challenges of advanced CMOS process from 2D to 3D
HH Radamson, Y Zhang, X He, H Cui, J Li, J ** of silicon through grafting a tailored molecular phosphorus precursor onto oxide-passivated silicon surfaces
T Alphazan, L Mathey, M Schwarzwalder… - Chemistry of …, 2016 - ACS Publications
Monolayer do** (MLD) of silicon substrates at the nanoscale is a powerful method to
provide controlled doses of dopants and defect-free materials. However, this approach …
provide controlled doses of dopants and defect-free materials. However, this approach …
FinFET with encased air-gap spacers for high-performance and low-energy circuits
AB Sachid, YM Huang, YJ Chen… - IEEE Electron …, 2016 - ieeexplore.ieee.org
We experimentally demonstrate n-channel bulk FinFET with encased air-gap spacers.
Encased air gap in the spacer region is formed by depositing carbon sidewalls, encasing …
Encased air gap in the spacer region is formed by depositing carbon sidewalls, encasing …
Design and analysis of analog performance of dual-k spacer underlap N/P-FinFET at 12 nm gate length
Among the multigate structures, FinFET is emerging as a promising candidate due to its
better gate electrostatic control and ease of manufacturability. However, loss of gate …
better gate electrostatic control and ease of manufacturability. However, loss of gate …