With the ever-increasing speed of integrated circuits, violations of the performance
specifications are becoming a major factor affecting the product quality level. The need for …

FIRE is a novel Fault-Independent algorithm for combinational REdundancy identification.
The algorithm is based on a simple concept that a fault which requires a conflict as a …

This paper presents a new static logic implication algorithm. An improved implication
procedure that fully takes advantage of the special context of static implication, the iterative …

We give two theorems for identifying untestable faults in sequential circuits. The first, the
single-fault theorem, states that if a single fault in a combinational array is untestable then …

This chapter presents both exact and heuristic two-level logic minimization algorithms. For
exact logic minimization, it shows various techniques to reduce the complexity of covering …

Previous solutions to the difficult problem of identifying sequential redundancy are either
based on incorrect theoretical results, or rely on unrealistic simplifying assumptions, or are …

A new technique called input reduction is proposed for built-in self test (BIST) test pattern
generator (TPG) design and test set compaction. This technique analyzes the circuit function …

Simulation-based test vector generators require much less computer time than deterministic
ATPG but they generate longer test sequences and sometimes achieve lower fault …

The security of logic locking has been extensively examined under the threat model that
assumes the availability of an activated IC. Recently, structural attacks such as ones based …

This paper describes a new technique to design efficient test pattern generators (TPGs) for
built-in self-test (BIST). The proposed technique identifies compatible circuit inputs that can …